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The timer A module can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/
capture interrupt (TAINT). TAOVF is interrupt level IRQ0, vector E0H. TAINT also belongs to interrupt level IRQ0,
but is assigned the separate vector address, DEH.
A timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. A
timer A match/capture interrupt, TAINT pending condition is also cleared by hardware when it has been serviced.
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The timer A module can generate an interrupt: the timer A match interrupt (TAINT). TAINT belongs to interrupt
level IRQ0, and is assigned the separate vector address, DEH.
When timer A measure interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically
by hardware.
In interval timer mode, a match signal is generated and TAOUT is toggled when the counter value is identical to
the value written to the TA reference data register, TADATA. The match signal generates a timer A match interrupt
(TAINT, vector DEH) and clears the counter.
If, for example, you write the value 10H to TADATA and 0AH to TACON, the counter will increment until it reaches
10H. At this point, the TA interrupt request is generated, the counter value is reset, and counting resumes.
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Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
TAPWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value
written to the timer A data register. In PWM mode, however, the match signal does not clear the counter. Instead,
it runs continuously, overflowing at FFH, and then continues incrementing from 00H.
Although you can use the match signal to generate a timer A overflow interrupt, interrupts are not typically used in
PWM-type applications. Instead, the pulse at the TAPWM pin is held to Low level as long as the reference data
value is
less than or equal to
(
≤
) the counter value and then the pulse is held to High level for as long as the data
value is
greater than
( > ) the counter value. One pulse width is equal to t
256 .
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In capture mode, a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value
into the TA data register. You can select rising or falling edges to trigger this operation.
Timer A also gives you capture input source: the signal edge at the TACAP pin. You select the capture input by
setting the value of the timer A capture input selection bit in the port 3 control register, P3CON, (set 1, bank 1,
E8H). When P3CONL.7.6 is 00, the TACAP input or normal input is selected. When P3CON.7.6 is set to 10,
normal output is selected.
Both kinds of timer A interrupts can be used in capture mode: the timer A overflow interrupt is generated whenever
a counter overflow occurs; the timer A match/capture interrupt is generated whenever the counter value is loaded
into the TA data register.
By reading the captured data value in TADATA, and assuming a specific value for the timer A clock frequency, you
can calculate the pulse width (duration) of the signal that is being input at the TACAP pin.