參數(shù)資料
型號(hào): TB28F400B5T80
廠商: INTEL CORP
元件分類(lèi): DRAM
英文描述: SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT
中文描述: 512K X 8 FLASH 5V PROM, 80 ns, PDSO44
封裝: 0.525 X 1.110 INCH, PLASTIC, SOP-44
文件頁(yè)數(shù): 29/38頁(yè)
文件大?。?/td> 501K
代理商: TB28F400B5T80
E
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V
CC
= 5.0 V, T = +25 °C. These currents are valid for all
product versions (packages and speeds).
2. I
CCES
is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of
I
CCES
and I
CCR
.
3. Block erases and word/byte program operations are inhibited when V
PP
= V
PPLK
, and not guaranteed in the range between
V
PPH
1 and V
PPLK
.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces I
CCR
to less than 1 mA typical, in static operation.
6. CMOS Inputs are either V
CC
± 0.2 V or GND ± 0.2 V. TTL Inputs are either V
IL
or V
IH
.
SMART 5 BOOT BLOCK MEMORY FAMILY
29
ADVANCE INFORMATION
TEST POINTS
INPUT
OUTPUT
1.5
3.0
0.0
1.5
0599-10
NOTE:
AC test inputs are driven at 3.0 V for a logic “1” and 0.0 V for a logic “0.” Input timing begins, and output timing ends, at 1.5 V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 11. High Speed Test Waveform
TEST POINTS
INPUT
OUTPUT
2.0
0.8
0.8
2.0
2.4
0.45
0599-11
NOTE:
AC test inputs driven at V
(2.4 V
TTL
) for logic “1” and V
(0.45 V
) for logic “0.” Input timing begins at V
IH
(2.0 V
TTL
) and V
IL
(0.8 V
TTL
) . Output timing ends at V
IH
and V
IL
. Input rise and fall times (10% to 90%) <10 ns.
Figure 12. Standard Test Waveform
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