參數(shù)資料
型號(hào): TB28F004S5-100
廠商: INTEL CORP
元件分類(lèi): DRAM
英文描述: BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
中文描述: 512K X 8 FLASH 5V PROM, 100 ns, PDSO44
封裝: 13.30 X 28.20 MM, PLASTIC, SOP-44
文件頁(yè)數(shù): 24/37頁(yè)
文件大?。?/td> 611K
代理商: TB28F004S5-100
BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY
E
24
PRODUCT PREVIEW
SR.7 =
0
1
Start
Write 60H
Write D0H
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
1
0
Read Status Register
Data (See Above)
1
0
Read Status Register
V
PP
Range Error
Bus
Operation
Command
Comments
Standby
Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Bus
Operation
Command
Comments
Write
Write
Clear Block
Lock-Bits Setup
Data = D0H
Addr = X
Read
Data = 60H
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write FFH after the clear block lock-bits operation to place device in
read array mode.
Standby
SR.3 =
SR.5 =
Clear Block Lock-Bits
Error
Clear Block Lock-Bits
Successful
Clear Block
Lock-Bits Confirm
Status Register Data
Standby
Check SR.5
1 = Clear Block Lock Bits Error
0
1
Device Protect Error
SR.1 =
1
0
SR.4,5 =
Command Sequence
Error
Check SR.4,5
Both 1 = Command Sequence Error
Standby
Check SR.1
1 = Device Protect Detect
RP# = V
,
Master Lock-Bit Is Set
Check SR.3
1 = V
PP
Error Detect
Figure 11. Clear Block Lock-Bits Flowchart
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