參數(shù)資料
型號: TAS5707PHP
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP48
封裝: 7 X 7 MM, GREEN, PLASTIC, HTQFP-48
文件頁數(shù): 54/57頁
文件大?。?/td> 1000K
代理商: TAS5707PHP
SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009
www.ti.com
PIN FUNCTIONS
PIN
TYPE
5-V
TERMINATION
DESCRIPTION
(1)
TOLERANT
(2)
NAME
NO.
AGND
30
P
Analog ground for power stage
AVDD
13
P
3.3-V analog power supply
AVSS
9
P
Analog 3.3-V supply ground
BST_A
4
P
High-side bootstrap supply for half-bridge A
BST_B
43
P
High-side bootstrap supply for half-bridge B
BST_C
42
P
High-side bootstrap supply for half-bridge C
BST_D
33
P
High-side bootstrap supply for half-bridge D
DVDD
27
P
3.3-V digital power supply
DVSSO
17
P
Oscillator ground
DVSS
28
P
Digital ground
FAULT
14
DO
Backend error indicator. Asserted LOW for over temperature, over
current, over voltage, and under voltage error conditions. De-asserted
upon recovery from error condition.
GND
29
P
Analog ground for power stage
GVDD_OUT
5, 32
P
Gate drive internal regulator output
LRCLK
20
DI
5-V
Pulldown
Input serial audio data left/right clock (sample rate clock)
MCLK
15
DI
5-V
Pulldown
Master clock input
NC
8
No connection
OC_ADJ
7
AO
Analog overcurrent programming. Requires resistor to ground.
OSC_RES
16
AO
Oscillator trim resistor. Connect an 18.2-k
1% resistor to DVSSO.
OUT_A
1
O
Output, half-bridge A
OUT_B
46
O
Output, half-bridge B
OUT_C
39
O
Output, half-bridge C
OUT_D
36
O
Output, half-bridge D
PDN
19
DI
5-V
Pullup
Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the noise shaper and initiating PWM stop
sequence.
PGND_AB
47, 48
P
Power ground for half-bridges A and B
PGND_CD
37, 38
P
Power ground for half-bridges C and D
PLL_FLTM
10
AO
PLL negative loop filter terminal
PLL_FLTP
11
AO
PLL positive loop filter terminal
PVDD_A
2, 3
P
Power supply input for half-bridge output A
PVDD_B
44, 45
P
Power supply input for half-bridge output B
PVDD_C
40, 41
P
Power supply input for half-bridge output C
PVDD_D
34, 35
P
Power supply input for half-bridge output D
RESET
25
DI
5-V
Pullup
Reset, active-low. A system reset is generated by applying a logic low
to this pin. RESET is an asynchronous control signal that restores the
DAP to its default conditions, and places the PWM in the hard mute
state (tristated).
SCL
24
DI
5-V
I2C serial control clock input
SCLK
21
DI
5-V
Pulldown
Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
SDA
23
DIO
5-V
I2C serial control data interface input/output
SDIN
22
DI
5-V
Pulldown
Serial audio data input. SDIN supports three discrete (stereo) data
formats.
(1)
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2)
All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic
levels if the pins are left unconnected (pullups
→ logic 1 input; pulldowns → logic 0 input).
6
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5707 TAS5707A
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