參數(shù)資料
型號: TAS5706APAPRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
封裝: 10 X 10 MM, GREEN, PLASTIC, HTQFP-64
文件頁數(shù): 25/71頁
文件大小: 1554K
代理商: TAS5706APAPRG4
Single-Byte Write
A6
A5
A4
A3
A2
A1
A0
R/W ACK A7
A6
A5
A4
A3
A2
A1
A0
ACK
D7
D6
D5
D4
D3
D2
D1
D0 ACK
Start
Condition
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
DataByte
T0036-01
Multiple-Byte Write
D7
D0 ACK
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress
LastDataByte
A6
A5
A1
A0 R/W ACK A7
A5
A1
A0
ACK D7
ACK
Start
Condition
Acknowledge
FirstDataByte
A4
A3
A6
OtherDataBytes
ACK
Acknowledge
D0
D7
D0
T0036-02
www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The
TAS5706A also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by
data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place,
and the data for all 16 subaddresses is successfully received by the TAS5706A. For I2C sequential write
transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted,
before a stop or start is transmitted, determines how many subaddresses are written. As was true for random
addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data
is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is
accepted; only the incomplete data is discarded.
As shown in Figure 40, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device
address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the
address byte or bytes corresponding to the TAS5706A internal memory address being accessed. After receiving
the address byte, the TAS5706A again responds with an acknowledge bit. Next, the master device transmits the
data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5706A
again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the
single-byte data write transfer.
Figure 40. Single-Byte Write Transfer
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 41. After receiving each data byte, the
TAS5706A responds with an acknowledge bit.
Figure 41. Multiple-Byte Write Transfer
Copyright 2009, Texas Instruments Incorporated
31
Product Folder Link(s): TAS5706A TAS5706B
相關(guān)PDF資料
PDF描述
TAS5706APAPR 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
TAS5706APAP 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
TAS5706PAPRG4 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
TAS5706PAPR 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
TAS5706PAP 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
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