
M1
M2
RESET
SD
OTW2
AGND
OC_ADJ
VREG
VDD
GVDD_A
M3
GND
INPUT_D
OUT_A
GND_A
PVDD_A
BST_A
GVDD_A
PWM
ACTIVITY
DETECTOR
GVDD_C
GVDD_B
INPUT_C
OUT_B
GND_B
PVDD_B
BST_B
GVDD_B
GVDD_D
GVDD_C
OUT_C
GND_C
PVDD_C
BST_C
GVDD_D
OUT_D
GND_D
PVDD_D
BST_D
INPUT_B
INPUT_A
PVDD_X
OUT_X
GND_X
TIMING
CONTROL
GATE-DRIVE
TIMING
CONTROL
GATE-DRIVE
TIMING
CONTROL
GATE-DRIVE
TIMING
CONTROL
GATE-DRIVE
PWM
RECEIVER
PWM
RECEIVER
PWM
RECEIVER
PWM
RECEIVER
+
-
A
N
A
L
O
G
C
O
M
P
A
R
A
T
O
R
M
U
X
+
-
+
-
+
-
P
R
O
T
E
C
T
IO
N
&
I/
O
L
O
G
IC
VI_CM
STARTUP
CONTROL
POWER-UP
RESET
TEMP
SENSE
OVER-LOAD
PROTECTION
PPSC
CB3C
UVP
CURRENT
SENSE
VREG
C_STARTUP
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
A
N
A
L
O
G
IN
P
U
T
M
U
X
AGC
PSU_REF
4
PVDD_X
4
GND
OTW1
READY
CLIP
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SLAS710 – JUNE 2010
FUNCTIONAL BLOCK DIAGRAM
Copyright 2010, Texas Instruments Incorporated
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