參數(shù)資料
型號(hào)： TAS5518PAG
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 56/105頁(yè)
文件大?。?/td> 1514K
代理商： TAS5518PAG
Electrical Specifications
46
SLES115 — August 2004
TAS5518
3.4
Electrical Characteristics Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
V
High level output voltage
3.3 V TTL and 5 V(6) tolerant
IOH = 4 mA
2.4
V
VOH
High-level output voltage
1.8-V LVCMOS (XTL_OUT)
IOH = 0.55 mA
1.44
V
Low level output voltage
3.3-V TTL and 5 V(6) tolerant
IOL = 4 mA
0.5
V
VOL
Low-level output voltage
1.8-V LVCMOS (XTL_OUT)
IOL = 0.75 mA
0.5
V
IOZ
High-impedance output current
3.3-V TTL
±20
A
3.3-V TTL
VI = VIL
±1
IIL
Low-level input current
1.8-V LVCMOS (XTL_IN)
VI = VIL
±1
A
IIL
Low level input current
5 V tolerant(5)
VI = 0 V DVDD = 3 V
±1
A
3.3-V TTL
VI = VIH
±1
IIH
High-level input current
1.8-V LVCMOS (XTL_IN)
VI = VIH
±1
A
IIH
High level input current
5 V tolerant(5)
VI = 5.5 V DVDD = 3 V
±1
A
Fs = 48 kHz
140
Digital supply voltage DVDD
Fs = 96 kHz
150
mA
I
Input supply current
Digital supply voltage, DVDD
Fs = 192kHz
155
mA
IDD
Input supply current
Power down
8
Analog supply voltage AVDD
Normal
6
mA
Analog supply voltage, AVDD
Power down
1
mA
NOTES: 5. 5-V tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4.
6. 5-V tolerant outputs are SCL and SDA
3.5
PWM Operation at Recommended Operating Conditions Over 05C to 705C
PARAMETER
TEST CONDITIONS
MODE
VALUE
UNITS
32-kHz data rate ±4%
12 x sample rate
384
kHz
Output sample rate 1X – 8 x over sampled
44.1-, 88.2-, 176.4-kHz data rate ±4%
8, 4, and 2 x sample rate
352.8
kHz
Output sample rate 1X 8 x over sampled
48, 96, 192 kHz data rate ±4%
8, 4, and 2 x sample rate
384
kHz
3.6
Switching Characteristics
3.6.1 Clock Signals Over Recommended Operating Conditions (Unless Otherwise
Noted)
3.6.1.1
PLL Input Parameters and External Filter Components{
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
fXTALI
Frequency, XTAL IN
Only use 13.5-MHz crystal ≤1000 ppm
13.5
MHz
fMCLKI
Frequency, MCLK (1 / tcyc2)
2
50
MHz
MCLK duty cycle duty cycle
40%
50%
60%
MCLK minimum high time
≥2-V MCLK = 49.152 MHz, Within the min
and max duty cycle constraints
5
ns
MCLK minimum low time
≤0.8-V MCLK = 49.152 MHz,
Within the min and max duty cycle constraints
5
ns
LRCLK allowable drift before LRCLK reset
10 MCLKs
External PLL filter cap C1
SMD 0603 Y5V
100
nF
External PLL filter cap C2
SMD 0603 Y5V
10
nF
External PLL filter resistor R
SMD 0603, metal film
200
External VRA_PLL decoupling
SMD, Y5V
100
nF
See the TAS5518 Example Application Schematic section.
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