參數(shù)資料
型號: TAS5504PAGRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 63/96頁
文件大小: 1216K
代理商: TAS5504PAGRG4
Serial Control I2C Register Summary
59
SLES123 October 2004
TAS5504
I2C
SUBADDRESS
DEFAULT STATE
DESCRIPTION OF CONTENTS
REGISTER FIELDS
TOTAL
BYTES
0x5F0x7A
RESERVED
0x7B0x88
20/Reg
See the next section
Channels 3 and 4 biquad filter
coefficient
All biquads = All pass
Loudness biquad coefficient b0
0x00, 0x00, 0xD5, 0x13
Loudness biquad coefficient b1
0x00, 0x00, 0x00, 0x00
0x95
20
Loudness biquad
Loudness biquad coefficient b2
0x0F, 0xFF, 0x2A, 0xED
0x95
20
Loudness biquad
Loudness biquad coefficient a0
0x00, 0xFE, 0x50, 0x45
Loudness biquad coefficient a1
0x0F, 0x81, 0xAA, 0x27
0x96
4
DRC1 control channels 1, 2,
and 3
DRC1 control channels 1, 2, and 3
DRC1 disabled in channels 1, 2,
and 3
0x97
4
DRC2 Ch 4 Control
DRC1 control channel 4
DRC2 disabled (channel 4)
0x98
8
Channels 1, 2, and 3,
DRC1 energy
0.0041579
0x98
8
Channels 1, 2, 3, and 4,
DRC1 (1 energy)
0.9958421
Channels 1, 2, and 3,
DRC1 threshold (T1) – upper 4 bytes
0x00, 0x00, 0x00, 0x00
0x99
16
,,
,
DRC1 threshold T1
DRC1 threshold (T1) – lower 4 bytes
0x0B, 0x20, 0xE2, 0xB2
0x99
16
Channels 1, 2, and 3,
DRC1 threshold (T2) – upper 4 bytes
0x00, 0x00, 0x00, 0x00
,,
,
DRC1 thresholdT2
DRC1 threshold (T2) – lower 4 bytes
0x06, 0xF9, 0xDE, 0x58
Channels 1, 2, and 3,
DRC1 slope k0
DRC1 slope (k0)
0x0F, 0xC0, 0x00, 0x00
0x9A
12
Channels 1, 2, and 3,
DRC1 slope k1
DRC1 slope (k1)
0x0F, 0xC0, 0x00, 0x00
Channels 1, 2, and 3,
DRC1 slope k2
DRC1 slope (k2)
0x0F, 0x90, 0x00, 0x00
Channels 1, 2, and 3,
DRC1 offset 1 (O1) – upper 4 bytes
0x00, 0x00, 0xFF, 0xFF
0x9B
16
,,
,
DRC1 offset 1
DRC1 offset 1 (O1) – lower 4 bytes
0xFF, 0x82, 0x30, 0x98
0x9B
16
Channels 1, 2, and 3,
DRC1 offset 2 (O2) – upper 4 bytes
0x00, 0x00, 0x00, 0x00
,,
,
DRC1 offset 2
DRC1 offset 2 (O2) – lower 4 bytes
0x01, 0x95, 0xB2, 0xC0
Channels 1, 2, and 3,
DRC1 attack
0x00, 0x00, 0x88, 0x3F
0x9C
16
Channels 1, 2, and 3,
DRC1 (1 Attack)
DRC1 (1 – Attack)
0x00, 0x7F, 0x77, 0xC0
0x9C
16
Channels 1, 2, and 3,
DRC1 Delay
DRC1 delay
0x00, 0x00, 0x00, 0xAE
Channels 1, 2, 3, and 3,
DRC1 (1 Delay)
DRC1 (1 – Delay)
0x00, 0x7F, 0xFF, 0x51
0x9D
8
Ch 4 DRC2 energy
DRC2 energy
0x00, 0x00, 0x88, 0x3F
0x9D
8
Ch 4 DRC2 (1 Energy)
DRC2 (1 – Energy)
0x00, 0x7F, 0x77, 0xC0
CH 4 DRC2 threshold T1
DRC2 threshold (T1) – upper 4 bytes
0x00, 0x00, 0x00, 0x00
0x9E
16
CH 4 DRC2 threshold T1
DRC2 threshold (T1) – lower 4 bytes
0x0B, 0x20, 0xE2, 0xB2
0x9E
16
CH 4 DRC2 threshold T2
DRC2 threshold (T2) – upper 4 bytes
0x00, 0x00, 0x00, 0x00
CH 4 DRC2 threshold T2
DRC2 threshold (T2) – lower 4 bytes
0x06, 0xF9, 0xDE, 0x58
Ch 4 DRC2 slope k0
DRC2 slope (k0)
0x00, 0x40, 0x00, 0x00
0x9F
12
Ch 4 DRC2 slope k1
DRC2 slope (k1)
0x0F, 0xC0, 0x00, 0x00
0x9F
12
Ch 4 DRC2 slope k2
DRC2 slope (k2)
0x0F, 0x90, 0x00, 0x00
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