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參數(shù)資料
| 型號： | TAS5342DDVG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 200 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO44 |
| 封裝： | GREEN, PLASTIC, HTSSOP-44 |
| 文件頁數(shù)： | 16/29頁 |
| 文件大?。?/td> | 866K |
| 代理商： | TAS5342DDVG4 |
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Overtemperature Protection
DEVICE RESET
Undervoltage Protection (UVP) and Power-On
SLAS557B – SEPTEMBER 2007 – REVISED OCTOBER 2007
PPSC detection is enabled in BTL and PBTL output
VDD or GVDD_X pin results in all half-bridge outputs
configurations, the detection is not performed in SE
immediately being set in the high-impedance (Hi-Z)
mode. To make sure not to trip the PPSC detection
state and SD being asserted low. The device
system it is recommended not to insert resistive load
automatically resumes operation when all supply
to GND_X or PVDD_X.
voltages have increased above the UVP threshold.
The TAS5342 has a two-level temperature-protection
Two reset pins are provided for independent control
system that asserts an active-low warning signal
of half-bridges A/B and C/D. When RESET_AB is
(OTW)
when
the
device
junction
temperature
asserted low, all four power-stage FETs in half--
exceeds 125
°C (nominal) and, if the device junction
bridges A and B are forced into a high-impedance
temperature exceeds 155
°C (nominal), the device is
(Hi-Z) state. Likewise, asserting RESET_CD low
put into thermal shutdown, resulting in all half-bridge
forces all four power-stage FETs in half-bridges C
outputs being set in the high-impedance (Hi-Z) state
and D into a high-impedance state. Thus, both reset
and SD being asserted low. OTE is latched in this
pins are well suited for hard-muting the power stage if
case. To clear the OTE latch, either RESET_AB or
needed.
RESET_CD must be asserted. Thereafter, the device
In BTL modes, to accommodate bootstrap charging
resumes normal operation.
prior to switching start, asserting the reset inputs low
enables weak pulldown of the half-bridge outputs. In
the SE mode, the weak pulldowns are not enabled,
Reset (POR)
and it is therefore recommended to ensure bootstrap
The UVP and POR circuits of the TAS5342 fully
capacitor charging by providing a low pulse on the
protect
the
device
in
any
power-up/down
and
PWM inputs when reset is asserted high.
brownout situation. While powering up, the POR
Asserting either reset input low removes any fault
circuit resets the overload circuit (OLP) and ensures
information to be signalled on the SD output, i.e., SD
that all circuits are fully operational when the
is forced high.
GVDD_X and VDD supply voltages reach stated in
the
Electrical
Characteristics
Table.
Although
A rising-edge transition on either reset input allows
GVDD_X and VDD are independently monitored, a
the device to resume operation after an overload
supply voltage drop below the UVP threshold on any
fault. To ensure thermal reliability, the rising edge of
reset must occur no sooner than 4ms after the falling
edge of SD.
Copyright 2007, Texas Instruments Incorporated
23
Product Folder Link(s): TAS5342
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TAS5342DDVR | 功能描述:音頻放大器 100W Class D Stereo Power Stage RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TAS5342DDVRG4 | 功能描述:音頻放大器 100W Class D Stereo Power Stage RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TAS5342L | 制造商:TI 制造商全稱:Texas Instruments 功能描述:100 W STEREO DIGITAL AMPLIFIER POWER STAGE |
| TAS5342LA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:100 W STEREO DIGITAL AMPLIFIER POWER STAGE |
| TAS5342LAADDVR | 制造商:Texas Instruments 功能描述:Class D Amplifier |
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