• 參數(shù)資料
    型號: TAS5342ADDV
    廠商: TEXAS INSTRUMENTS INC
    元件分類: 音頻/視頻放大
    英文描述: 100 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO44
    封裝: GREEN, PLASTIC, HTSSOP-44
    文件頁數(shù): 15/27頁
    文件大?。?/td> 835K
    代理商: TAS5342ADDV
    Overtemperature Protection
    DEVICE RESET
    Undervoltage Protection (UVP) and Power-On
    SLAS623 – NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com
    PPSC detection is enabled in BTL and PBTL output
    VDD or GVDD_X pin results in all half-bridge outputs
    configurations, the detection is not performed in SE
    immediately being set in the high-impedance (Hi-Z)
    mode. To make sure not to trip the PPSC detection
    state and SD being asserted low. The device
    system it is recommended not to insert resistive load
    automatically resumes operation when all supply
    to GND_X or PVDD_X.
    voltages have increased above the UVP threshold.
    The
    TAS5342A
    has
    a
    two-level
    Two reset pins are provided for independent control
    temperature-protection
    system
    that
    asserts
    an
    of half-bridges A/B and C/D. When RESET_AB is
    active-low warning signal (OTW) when the device
    asserted low, all four power-stage FETs in half--
    junction temperature exceeds 125°C (nominal) and, if
    bridges A and B are forced into a high-impedance
    the device junction temperature exceeds 155°C
    (Hi-Z) state. Likewise, asserting RESET_CD low
    (nominal), the device is put into thermal shutdown,
    forces all four power-stage FETs in half-bridges C
    resulting in all half-bridge outputs being set in the
    and D into a high-impedance state. Thus, both reset
    high-impedance (Hi-Z) state and SD being asserted
    pins are well suited for hard-muting the power stage if
    low. OTE is latched in this case. To clear the OTE
    needed.
    latch, either RESET_AB or RESET_CD must be
    In BTL modes, to accommodate bootstrap charging
    asserted. Thereafter, the device resumes normal
    prior to switching start, asserting the reset inputs low
    operation.
    enables weak pulldown of the half-bridge outputs. In
    the SE mode, the weak pulldowns are not enabled,
    and it is therefore recommended to ensure bootstrap
    Reset (POR)
    capacitor charging by providing a low pulse on the
    The UVP and POR circuits of the TAS5342A fully
    PWM inputs when reset is asserted high.
    protect
    the
    device
    in
    any
    power-up/down
    and
    Asserting either reset input low removes any fault
    brownout situation. While powering up, the POR
    information to be signalled on the SD output, i.e., SD
    circuit resets the overload circuit (OLP) and ensures
    is forced high.
    that all circuits are fully operational when the
    GVDD_X and VDD supply voltages reach stated in
    A rising-edge transition on either reset input allows
    the
    Electrical
    Characteristics
    Table.
    Although
    the device to resume operation after an overload
    GVDD_X and VDD are independently monitored, a
    fault. To ensure thermal reliability, the rising edge of
    supply voltage drop below the UVP threshold on any
    reset must occur no sooner than 4ms after the falling
    edge of SD.
    22
    Copyright 2008, Texas Instruments Incorporated
    Product Folder Link(s): TAS5342A
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