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參數(shù)資料
| 型號： | TAS5261DKDRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 315 W, 1 CHANNEL, AUDIO AMPLIFIER, PDSO36 |
| 封裝： | GREEN, PLASTIC, HSSOP-36 |
| 文件頁數(shù)： | 24/25頁 |
| 文件大?。?/td> | 983K |
| 代理商： | TAS5261DKDRG4 |
www.ti.com
RECOMMENDED OPERATING CONDITIONS
AUDIO CHARACTERISTICS
SLES188 – AUGUST 2006
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
PVDD_x
Half-bridge supply voltage
0
50
52.5
V
GVDD_x
Gate-drive power supply
10.8(1)
12
13.2
V
VDD
Digital regulator supply voltage
10.8(1)
12
13.2
V
RL
Resistive load impedance, bridge-tied load (BTL)
4-16
RL
Resistive load impedance, BTL, ROC = 22k, PVDD = 50V, (no current limiting)
3
Minimum output filter inductance under both operating and short-circuit conditions,
LDEM
5
10
H
with appropriate OC_ADJ resistor value
fS
PWM frame rate
192
384
kHz
t(low)
Minimum low-state pulse duration per PWM frame, noise shaper enabled
50
ns
CBS
Bootstrap capacitor, selected value supports fs = 192 kHz to 384 kHz
33
nF
RBS
Bootstrap series resistor - 1/4 W
1.5
4.7
RCBS
Bootstrap snubber - 1/4 W
470
pF
Ultra-Fast Recovery Clamping Diode, Average forward current = 1A, Maximum
DCLMP
15
nS
repetitive reverse voltage = 200V (ES1D, mfg:Fairchild)
DTVS
Transient Voltage Suppressor, 600W @ 1mS (P6SMB62AT3, mfg: ON Semiconductor)
62
V
CPVDD
PVDD Close Decoupling Capacitor, two capacitors
100
nF
RAGND
AGND resistor - 1/4 W
3.3
R
Optional external pullup resistor to +3.3V or +5 V for SD and OTW
3.3
4.7
k
TJ
Junction temperature
0
125
°C
(1)
GVDD operation below 10.8 V significantly reduces efficiency of the output MOSFET stage and requires a larger heatsink. For the
purpose of noise margin, the UVP level is set lower to provide an increased noise margin, however, TI recommends a nominal dc
voltage of 12 V for GVDD.
Audio frequency = 1 kHz, PVDD_x = 50 V, GVDD_x = 12 V, VDD = 12 V, R
L = 8 , fs = 384 kHz, OC_ADJ = 22 k,
T
C= 75°C, output filter is LDEM = 10 H, CL = 1 F (unless otherwise noted). Audio performance is recorded as a chipset,
TAS5518 as front end with an effective modulation index of 96.1% and TAS5261 as the power stage. PCB and system
configuration are in accordance with recommended design guidelines.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RL = 8 , f = 1 kHz
125
PO
Unclipped power output
RL = 6 , f = 1 kHz
165
W
RL = 4 , f = 1 kHz
235
RL = 8 , f = 1 kHz, THD = 10%
165
RL = 6 , f = 1 kHz, THD = 10%
220
PO
Maximum power output
W
RL = 4 , f = 1 kHz, THD = 10%
315
RL = 3 , f = 1 kHz, CBC allowed
400
Total harmonic distortion + noise,
1 W to 125 W, RL=8
, AES17 filter,
THD+N
0.09
%
AES 17 filter
Unclipped
Ratio of 1-FFS to 0-FFS input,
SNR
Signal-to-noise ratio(1)
110
dB
A-weighted filter
DNR
Dynamic range
–60-dBFS input, A-weighted filter
110
dB
PWM switching frequency 384 kHz,
VOO
Output offset voltage
–15
15
mV
Measured on speaker terminals
Power dissipation due to idle losses
Pidle
PO = 0 W, Output switching(2)
2
W
(IPVDD_X)
(1)
SNR is calculated relative to the 0 dBFS input level.
(2)
Actual system idle losses are also affected by core losses of output inductors.
8
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