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Device Reset
Over Temperature (OTE) Protection
PWM Activity Detector
Under Voltage Protection (UVP) and
Modulation Index Setting
SLES188 – AUGUST 2006
For
added
flexibility,
the
OC
threshold
is
VDD or GVDD_x pin results in all half-bridge outputs
programmable within a limited range using a single
immediately being set in the high-impedance state
external resistor connected between the OC_ADJ pin
(Hi-Z) and SD being asserted low. The device
and AGND. It should be noted that a properly
automatically resumes operation when all supply
functioning
overcurrent
detector
assumes
the
voltages have increased above the UVP threshold.
presence of a properly designed demodulation filter
at the power-stage output. Short-circuit protection is
not provided directly at the output pins of the power
When RESET is asserted low, the output FETs in all
stage but only on the speaker terminals (after the
half bridges are forced into a high-impedance state
demodulation filter). It is required to follow certain
(Hi-Z). During this reset time, a resistor is connected
guidelines when selecting the OC threshold and an
between OUT_x and PGND pins, in order to charge
appropriate demodulation inductor.
the bootstrap capacitor.
Asserting
RESET
input
low
removes
fault
information. A rising-edge transition on the reset
The
TAS5261
has
a
two-level,
input allows the device to resume operation after an
temperature-protection
system
that
asserts
an
overload fault.
active-low warning signal (OTW) when the device
junction temperature exceeds the OTW level stated
in the parametric table. If the device junction
temperature exceeds the OTE level stated in the
The PWM Activity Detector logic monitors individual
parametric table, the device is put into thermal
PWM inputs. If one or more inputs are stuck in either
shutdown, resulting in all half-bridge outputs being
a high state or a low state for more than a defined
set in the high-impedance state (Hi-Z) and SD being
length of time, the entire device is shut down.
asserted low. OTE is latched in this case. To clear
The PWM Activity Detector is not latched and normal
the OTE latch, reset must be asserted. Thereafter,
operation resumes when PWM activity is present on
the device resumes normal operation.
the PWM inputs. When an invalid PWM frame is
detected,
the
PWM
Activity
Detector
responds
immediately (no delay). The TAS5261 resumes
Power-On Reset (POR)
operation as soon as valid PWM signals are present.
The UVP and POR circuits of the TAS5261 fully
The PWM Activity Detector is reported as a low on
protect the device in any power-up/down and
the SD pin.
brownout situation. While powering up, the POR
circuit resets the overload circuit (OLP) and ensures
that all circuits are fully operational when the
GVDD_x and VDD supply voltages reach the UVP
96.1%
is
the
recommended
setting
for
the
level
stated
in
the
parametric
table.
Although
modulation index limit of the PWM when driving the
GVDD_x and VDD are independently monitored, a
TAS5261. The following shows modulation index
supply-voltage drop below the UVP threshold on any
limit registers and setting value in hexadecimal for TI
modulators.
TAS5508/TAS5518: 0x16h at 04h
TAS5086: 0x10h at 04h
18