參數資料
型號: TAS5132DDVRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 50 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO44
封裝: GREEN, PLASTIC, HTSSOP-44
文件頁數: 2/26頁
文件大?。?/td> 574K
代理商: TAS5132DDVRG4
www.ti.com
ELECTRICAL CHARACTERISTICS
SLES190 – DECEMBER 2006
R
L= 8 , FPWM = 384 kHz (unless otherwise noted). All performance is in accordance with recommended operating
conditions, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal Voltage Regulator and Current Consumption
Voltage regulator, only used as a
VREG
VDD = 12 V
3
3.3
3.6
V
reference node
Operating, 50% duty cycle
6
9
IVDD
VDD supply current
mA
Idle, reset mode
5.5
8
50% duty cycle
3.6
5.5
IGVDD_X
Gate supply current per half-bridge
mA
Reset mode
1.0
2.0
50% duty cycle, without output filter or load
9
15
mA
IPVDD_X
Half-bridge idle current
Reset mode, no switching
.1
.2
mA
Output Stage MOSFETs
TJ = 25°C, includes metallization resistance,
RDSon,LS
Drain-to-source resistance, LS
140
155
m
GVDD = 12 V
TJ = 25°C, includes metallization resistance,
RDSon,HS
Drain-to-source resistance, HS
140
155
m
GVDD = 12 V
I/O Protection
Undervoltage protection limit,
Vuvp,G
9.6
V
GVDD_X, voltage rising
Undervoltage protection limit,
Vuvp,G
9.2
V
GVDD_X, voltage falling
Puts device into RESET when BST
BSTuvpF
6.2
V
voltage falls below limit
Brings device out of RESET when
BSTuvpR
6.6
V
BST voltage rises above limit
OTW(1)
Overtemperature warning
125
°C
Temperature drop needed below
OTWHYST(1)
OTW temperature for OTW to be
25
°C
inactive after the OTW event
OTE(1)
Overtemperature error
155
°C
OTE-
OTE-OTW differential
30
°C
OTWdifferential(1)
A reset event must occur for SD to
OTEHYST(1)
be released following an OTE
30
°C
event.
OLPC
Overload protection counter
FPWM = 384 kHz
1.25
ms
Resistor—programmable, max. current,
IOC
Overcurrent limit protection
4.0
5.0
6.0
A
ROCP = 22 k
IOCT
Overcurrent response time
150
ns
ROCP
OC programming resistor range
Resistor tolerance = 5% for typical value; the
k
minimum resistance should not be less than
20
22
20k
.
Connected when RESET is active to provide
Internal pulldown resistor at the
RPD
bootstrap capacitor charge. Not used in SE
3.0
k
output of each half-bridge
mode
PWM Activity Detector, causes
PWM stopped and time measured for device
PAD
device reset when PWM input
10
25
S
to go into RESET (Output switching stopped)
signal is stopped.
(1)
Specified by design
10
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