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參數(shù)資料
| 型號： | TAS5132DDVR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 50 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO44 |
| 封裝： | GREEN, PLASTIC, HTSSOP-44 |
| 文件頁數(shù)： | 13/26頁 |
| 文件大小： | 574K |
| 代理商： | TAS5132DDVR |
www.ti.com
DEVICE RESET
Overtemperature Protection
Undervoltage Protection (UVP) and Power-On
SLES190 – DECEMBER 2006
Current
limiting
and
overload
protection
are
that all circuits are fully operational when the
independent
for
half-bridges
A
and
B
and,
GVDD_X and VDD supply voltages reach 9.6 V
respectively, C and D. That is, if the bridge-tied load
(typical).
Although
GVDD_X
and
VDD
are
between half-bridges A and B causes an overload
independently monitored, a supply voltage drop
fault, only half-bridges A and B are shut down.
below the UVP threshold on any VDD or GVDD_X
pin results in all half-bridge outputs immediately
OC-Adjust Resistor Values
Max. Current Before OC
being set in the high-impedance (Hi-Z) state and SD
(k
)
Occurs (A)
being
asserted
low.
The
device
automatically
22
5.2
resumes operation when all supply voltages have
27
4.6
increased above the UVP threshold.
30
4.2
33
3.8
42
3.2
Two reset pins are provided for independent control
47
2.9
of half-bridges A/B and C/D. When RESET_AB is
56
2.5
asserted low, all four power-stage FETs in half--
bridges A and B are forced into a high-impedance
69.8
2.0
(Hi-Z) state. Likewise, asserting RESET_CD low
forces all four power-stage FETs in half-bridges C
and D into a high-impedance state. Thus, both reset
pins are well suited for hard-muting the power stage
The TAS5132 has a two-level temperature-protection
if needed.
system that asserts an active-low warning signal
(OTW)
when
the
device
junction
temperature
In BTL modes, to accommodate bootstrap charging
exceeds 125
°C (nominal) and, if the device junction
prior to switching start, asserting the reset inputs low
temperature exceeds 155
°C (nominal), the device is
enables weak pulldown of the half-bridge outputs. In
put into thermal shutdown, resulting in all half-bridge
the SE mode, the weak pulldowns are not enabled,
outputs being set in the high-impedance (Hi-Z) state
and it is therefore recommended to ensure bootstrap
and SD being asserted low. OTE is latched in this
capacitor charging by providing a low pulse on the
case. To clear the OTE latch, both RESET_AB and
PWM inputs when reset is asserted high.
RESET_CD must be asserted. Thereafter, the device
resumes normal operation.
Asserting either reset input low removes any fault
information to be signalled on the SD output, i.e., SD
is forced high.
Reset (POR)
A rising-edge transition on either reset input allows
The UVP and POR circuits of the TAS5132 fully
the device to resume operation after an overload
protect the device in any power-up/down and
fault.
brownout situation. While powering up, the POR
circuit resets the overload circuit (OLP) and ensures
20
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