參數(shù)資料
型號(hào): TAS5121IDKDR
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 100 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO36
封裝: GREEN, PLASTIC, HSSOP-36
文件頁數(shù): 16/22頁
文件大小: 632K
代理商: TAS5121IDKDR
www.ti.com
PACKAGE DISSIPATION RATINGS
TAS5121I
SLES122 – SEPTEMBER 2004
ORDERING INFORMATION
TA
PACKAGE
TRANSPORT MEDIA
DESCRIPTION
–40
°C to 85°C
TAS5121IDKD
Tube
36-pin PSOP3
–40
°C to 85°C
TAS5121IDKDR
Tape and reel
36-pin PSOP3
RθJC
RθJA
PACKAGE
(
°C/W)
(
°C/W)
36-Pin DKD PSOP3
0.85
See (1)
(1)
The TAS5121I package is thermally enhanced for conductive cooling using an exposed metal pad area. It is impractical to use the
devices with the pad exposed to ambient air as the only heat sinking of the device.
Therefore RθJA, a system parameter that characterizes the thermal treatment, is provided in the Thermal Information section. This
information should be used as a reference to calculate the heat dissipation ratings for a specific application.
Terminal Functions
TERMINAL
FUNCTION(1)
DESCRIPTION
NAME
DKD
BST_A
22
P
High-side bootstrap (BST) supply, external resistor and capacitor to OUT_A required
BST_B
33
P
High-side bootstrap (BST) supply, external resistor and capacitor to OUT_B required
DGND
9, 14
P
I/O reference ground
DREG
8
P
Digital supply-voltage regulator-decoupling pin, 1-
F capacitor connected to DREG_RTN
DREG_RTN
5
P
Decoupling return pin
DVDD
12
P
I/O reference supply input: 100
to DREG, decoupled to GND, 0.1-F capacitor connected to
GND
1, 3, 16,
P
Power ground, connected to system GND
18, 21,
27, 28,
34
GVDD
6
P
Local GVDD decoupling pin
GVDD_A
19, 20
P
Gate-drive input voltage
GVDD_B
35, 36
P
Gate-drive input voltage
M1
10
I
Protection-mode selection pin, connect to GND
M2
11
I
Protection-mode selection pin, connect to DREG
M3
7
I
Output-mode selection pin; connect to GND
OTW
15
O
Overtemperature warning output, open-drain with internal pullup, asserted low when tempera-
ture exceeds 115
°C
OUT_A
25, 26
O
Output, half-bridge A
OUT_B
29, 30
O
Output, half-bridge B
PVDD_A
23, 24
P
Power supply input for half-bridge A
PVDD_B
31, 32
P
Power supply input for half-bridge B
PWM_AP
17
I
PWM input signal, half-bridge A
PWM_BP
2
I
PWM input signal, half-bridge B
RESET
4
I
Reset signal, active-low
SD
13
O
Shutdown signal for half-bridges A and B (open-drain with internal pullup)
(1)
I = input, O = Output, P = Power
3
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