參數(shù)資料
型號(hào)： TAS5110DAPR
廠商： Texas Instruments, Inc.
元件分類： 運(yùn)動(dòng)控制電子
英文描述： TRUE DIGITAL AUDIO AMPLIFIER TAS5110 PWM POWER OUTPUT STAGE
中文描述： 真正的數(shù)字音頻放大器TAS5110的PWM功率輸出級(jí)
文件頁(yè)數(shù)： 6/20頁(yè)
文件大?。?/td> 264K
代理商： TAS5110DAPR
TAS5110
SLES028A
–
MAY 2002
–
REVISED SEPTEMBER 2002
6
www.ti.com
Terminal Functions
TERMINAL
NAME
DAP
NO.
11
12
30
19
6
7, 8, 9
DAD
NO.
6
5
19
30
11
8, 9,
10
I/O
DESCRIPTION
BIAS_A
BIAS_B
BOOTSTRAPA
BOOTSTRAPB
DVDD
DVSS
I
I
Connect external resistor to DVSS.
Connect external resistor to DVSS.
Bootstrap capacitor pin for H-bridge A
Bootstrap capacitor pin for H-bridge B
3.3-V digital voltage supply for logic
Digital ground for logic is internally connected to PVSS. All three pins must be tied
together but not connected externally to PVSS. See Figure 5.
O
O
I
I
ERR1
ERR0
LDROUTA
3
4
31
14
13
18
O
O
O
Error/warning report indicator. This output is open drain with internal pullup resistor.
Error/warning report indicator. This output is open drain with internal pullup resistor.
Low voltage drop-out regulator output A (not to be used to supply current to external
circuitry)
LDROUTB
18
31
O
Low voltage drop-out regulator output B (not to be used to supply current to external
circuitry)
OUTPUTA
OUTPUTB
PVDDA1
PVDDA2
PVDDB1
PVDDB2
PVSS
PWDN
PWM_AM
PWM_AP
PWM_BP
PWM_BM
RESET
26, 27
22, 23
28, 29
32
20, 21
17
24, 25
13
2
1
16
15
14
22, 23
26, 27
20, 21
17
28, 29
32
24, 25
4
15
16
1
2
3
O
O
I
I
I
I
I
I
I
I
I
I
I
H-bridge output A
H-bridge output B
High voltage power supply, H-bridge A
High voltage power supply for low-dropout voltage regulator A-side
High voltage power supply, H-bridge B
High voltage power supply for low-dropout voltage regulator B-side
High voltage power supply ground
Power down = 0, normal mode = 1
PWM input A(
–
)
PWM input A(+)
PWM input B(+)
PWM input B(
–
)
Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFETs are
in low-low output state. Asserting the RESET signal low causes all fault conditions to be
cleared.
Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0, when
device is in shutdown mode the H-bridge MOSFETs are in low-low output state. The
latched output can be cleared by asserting the RESET signal. This output is open drain
with internal pullup resistor.
A filter capacitor must be added between VRFILT and DVSS pins.
SHUTDOWN
5
12
O
VRFILT
NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS50xx output pins, and never
left floating. Floating PWM input pins causes an illegal PWM input state signal to be asserted.
10
7
O
Dual pins: OUTPUTA, OUTPUTB, PVDDA1, and PVDDB1 must have both pins connected externally to the same point on the circuit board,
respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high-current DMOS output
devices. Failure to connect all the multiple pins to the same respective node results in excessive current flow in the internal bond wires
and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins connected to the same
node, respectively.
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