參數(shù)資料
型號(hào): TAS5110DAP
廠商: Texas Instruments, Inc.
元件分類: 運(yùn)動(dòng)控制電子
英文描述: TRUE DIGITAL AUDIO AMPLIFIER TAS5110 PWM POWER OUTPUT STAGE
中文描述: 真正的數(shù)字音頻放大器TAS5110的PWM功率輸出級(jí)
文件頁數(shù): 11/20頁
文件大小: 264K
代理商: TAS5110DAP
TAS5110
SLES028A
MAY 2002
REVISED SEPTEMBER 2002
11
www.ti.com
recommended operating conditions (maximum output power = 50 W (RMS), T
J
= 25
°
C)
thermal data
PARAMETER
MIN
NOM
MAX
UNIT
Shutdown junction temperature, TJ(SD)
Warning junction temperature, TJ(W)
150
°
C
125
°
C
Operating temperature TC
Operating temperature, TC
Commercial
0
25
70
°
C
Industrial
40
25
85
°
C
Thermal resistance junction-to-case,
θ
jc
Thermal resistance junction-to-ambient,
θ
ja
One of the most influential components on the thermal performance of a package is board design. In order to take full advantage of the heat
dissipating abilities of the PowerPAD packages, a board must be used that acts similar to a heat sink and allows for the use of the exposed (and
solderable), deep downset pad. See Appendix A of the
PowerPAD Thermally Enhanced Package
application note, TI literature number
SLMA002.
For both DAD and DAP packages.
2 oz trace and copper pad without solder
2 oz. trace and copper pad without solder
1.6
°
C/W
44.3
°
C/W
R
L
= 6
to 8
PARAMETER
MIN
NOM
MAX
UNIT
Digital
DVDD to DVSS
3
3.3
3.6
V
PVDDA2 to PVSS
16.5
22
26.5
Supply voltage
Regulator
PVDDB2 to PVSS
16.5
22
26.5
V
PVDDA2 to PVSS
10.5
16.5
PVDDB2 to PVSS
10.5
16.5
§
Connect LDROUTA to PVDDA2 and connect LDROUTB to PVDDB2. Under this condition, the H-bridge forward on-state resistance is increased.
This increases internal power dissipation. Maximum output power may need to be reduced to meet thermal conditions.
maximum available power at common load impedances for both DAP and DAD packages unclipped (0 dB)
level, test conditions described in the
Thermal Methodology for the 32-Pin DAD Package 50 W, 6-
Test
and
Thermal Methodology for the 32-Pin DAP Package 50 W, 6-
Test
sections
LOAD IMPEDANCE (
)
PVDAA1/PVDDB1 (VDC)
APPROXIMATE MAX OUTPUT POW-
ER (W)
50
THD+N AT MAX POWER AND 1 kHz
INPUT
< 10%
6
27
6
27
43
< 0.09%
8
27
34
< 0.09%
Dependent on board design and component selection.
static digital specifications
RESET, PWDN, PWM_AP, PWM_AM, PWM_BP, PWM_BM, T
J
= 25
°
C, DVDD = 3.3 V
PARAMETERS
MIN
MAX
UNIT
High-level input voltage, VIH
Low-level input voltage, VIL
Input leakage current
2
V
0.8
V
10
10
μ
A
ERR0, ERR1, SHUTDOWN, (open drain with internal pullup resistor) T
J
= 25
°
C, DVDD = 3.3 V)
PARAMETERS
MIN
MAX
UNIT
Internal pullup resistors from SHUTDOWN, ERR0, ERR1 to DVDD
15
k
Low-level output voltage (IO = 4 mA), VOL
0.4
V
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