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參數(shù)資料
| 型號： | TAS5076PFCRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | GREEN, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 21/64頁 |
| 文件大?。?/td> | 873K |
| 代理商： | TAS5076PFCRG4 |
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Architecture Overview
22
SLES090A—November 2003—Revised January 2004
TAS5076
REGISTER
SETTING
FUNCTION
0Ch
01h
TC delay channel 1
0Dh
49h
TC delay channel 2
0Eh
91h
TC delay channel 3
0Fh
39h
TC delay channel 4
10h
21h
TC delay channel 5
11h
69h
TC delay channel 6
These values must be reprogrammed every time RESET is asserted. RESET causes default values to be
loaded.
2.4.6 ABD Delay
A 5-bit value is used to delay the A PWM signals with respect to B PWM signals. The value is the same for
all channels. It can be programmed from 0 to 31 DCLK clock cycles. The default ABD value is 20 DCLK clock
cycles (10100). This value is mask programmable.
This value can be changed at any time through the serial control interface.
The optimum value for ABD delay depends on the final system. This value can be adjusted for better
performance with regard to dynamic range and THD. It is recommended that the following ABD delay value
be set instead of the default value. The ABD delay value in conjunction with the TC delay values delivers the
best performance in the TAS50765182 EVM board.
REGISTER
SETTING
FUNCTION
12h
1Dh
ABD delay
This value must be reprogrammed every time RESET is asserted. RESET causes the default value to be
loaded.
NOTE:
The performance of a PurePath Digital
amplifier system is optimized by setting the PWM
timing based upon the type of back-end device that is used and the layout. These values are
set during initialization using the I2C serial interface.
2.4.7 PWM/H-Bridge and Discrete H-Bridge Driver Interface
The TAS5076 provides six PWM outputs, which are designed to drive switching output stages (back-ends)
in both single-ended (SE) and H-bridge (bridge-tied load) configuration. The back ends can be monolithic
power stages (such as the TAS5110) or six discrete differential power stages using gate drivers (such as the
the TAS55182) and MOSFETs in single-ended or bridged configurations.
The TAS5110 device is optimized for bridge-tied load (BTL) configurations. These devices require a pure
differential PWM signal with a third signal (VALID) to control the MUTE state. In the MUTE state, the TAS5110
OUTA and OUTB are both low.
One Channel
of TAS5076
PWM_AP
PWM_AM
VALID
TAS5110
OUTA
OUTB
AP
AM
RESET
BP
BM
Speaker
PWM_BP
PWM_BM
Figure 212. PWM Outputs and H-Bridge Driven in BTL Configuration
PurePath Digital is a trademark of Texas Instruments.
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