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參數(shù)資料
| 型號： | TAS5066PAGRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 16/66頁 |
| 文件大?。?/td> | 1023K |
| 代理商： | TAS5066PAGRG4 |
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Architecture Overview
17
SLES089—January 2004
TAS5066
Because PDN is an asynchronous control signal, small clicks and pops can be produced during the application
(the leading edge) of this control. However, when PDN is released, the transition from the hard mute state back
to normal operation is performed synchronously using a quiet sequence.
If a completely quiet reset sequence is desired, MUTE must be applied before applying PDN.
2.2.2.1
Recovery Time Options
To support the requirements of various system configurations, the TAS5066 can come up to the normal state
after either a long (100 ms) or a short (5 ms) delay.
1.
In the first case, a slow system (95 ms to 100 ms) start-up occurs at the end of the power-down sequence
when:
RESET is high for at least 16 MCLK_IN periods before PDN goes high.
2.
Otherwise a fast (4 ms to 5 ms) start-up occurs.
NOTE: If MCLK_IN is not active when both of these signals are released high, then a fast
(4 ms to 5 ms) start-up occurs once MCLK_IN becomes active.
2.2.3 General Status Registers
The general status register is a read only register. This register provides an indication when a volume update
is in progress or one of the channels is inactive. The device id can be read using this register.
Volume update is in progress—Whenever a volume change is in progress due to a volume update
command or mute, this status bit is high.
Device identification code—The device identification code, 0 0000, is displayed.
No internal errors (all valid signals are high)—When there are no internal errors in the TAS5066 and all
outputs are valid, this status bit is high.
One or more valid signals are inactive—If low, one or more channels of the TAS5066 are not outputting data.
The Valid signals for those channels are inactive.
Inactive valid signals can be produced by one of these causes:
One or more of the clock signals are in error
Error recover is active (low)
The automute has silenced one or more channels that are receiving 0 inputs
Mute has been set
Volume control has been set to full attenuation
If this signal is high, the TAS5066 is outputting data on all channels.
2.2.4 Error Status Register
The error status register indicates historical information on control signal changes and clock errors. This
register latches these indications when they occur. The indications are cleared by writing a 00(Hex) to the
register.
This register is intended as a diagnostic tool to be used only when the system is not operating correctly. This
is because the error status bits are set when the data rate, serial data interface format, or master/slave mode
is changed. As a result, this register indicates an error condition even though the system is operating normally.
This register must be used only while diagnosing transient error conditions.
Any clock error or control signal terminal change which occurs since the last time the error status register was
cleared is displayed. In using this register, the first step is to initialize the device and verify that all of the clock
signals are active. Then this register must be cleared by writing a 00(Hex). At this point, the register indicates
any errors or control signal changes.
This register indicates an error condition by a high for the following conditions:
FS ERROR
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