參數(shù)資料
型號： TAS5036PFCR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 24/49頁
文件大小： 716K
代理商： TAS5036PFCR
Serial Control Interface Register Definitions
25
SLES044B—November 2002
TAS5036
3.1
General Status Register (x00)
Table 3–2. General Status Register (Read Only)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
-
No volume update is in progress.
1
-
Volume update is in progress.
-
0
-
Always 0
-
1
0
1
-
Device identification code
-
0
Any valid signal is inactive (see status register (X03)) (see Note 1).
-
1
No internal errors (all valid signals are high)
NOTE 1: This bit is reset automatically when all of the valid signals are active.
3.2
Error Status Register (x01)
Table 3–3. Error Status Register
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1
-
FS error has occurred
-
1
-
Control pin change has occurred
-
1
-
LRCLK error
-
1
-
MCLK_IN count error
-
1
-
DCLK phase error with respect to MCLK_IN
-
1
-
MCLK_IN phase error with respect to DCLK
-
1
PWM timing error
0
No errors—no control pins changed
NOTE 1: Write 00 hex to clear error indications in Error Status Register.
3.3
System Control Register 0 (x02)
Table 3–4. System Control Register 0
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
-
Normal mode (in slave mode—quad speed detected if MCLK_IN = 128 Fs)
0
1
-
Double speed
1
0
-
Quad speed
1
-
Illegal
-
0
-
Use de-emphasis pin controls
-
1
-
Use de-emphasis I2C controls
-
0
-
No de-emphasis
-
0
1
-
De-emphasis for Fs = 32 kHz
-
1
0
-
De-emphasis for Fs = 44.1 kHz
-
1
-
De-emphasis for Fs = 48 kHz
-
0
16 bit, MSB first; right justified
-
0
1
20 bit, MSB first; right justified
-
0
1
0
24 bit, MSB first; right justified
-
0
1
16-bit IIS
-
1
0
20-bit IIS
-
1
0
1
24-bit IIS
-
1
0
16-bit MSB first
-
1
16-bit DSP Frame
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