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參數(shù)資料
| 型號： | TAS5036IPFCR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR |
| 中文描述： | 六聲道數(shù)字音頻PWM處理器 |
| 文件頁數(shù)： | 26/49頁 |
| 文件大?。?/td> | 642K |
| 代理商： | TAS5036IPFCR |
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Architecture Overview
21
SLES044B
—
November 2002
TAS5036
2.4.7 PWM/H-Bridge and Discrete H-Bridge Driver Interface
The TAS5036 provides six PWM outputs, which are designed to drive switching output stages (back-ends)
in both single-ended (SE) and H-bridge (bridge tied load) configuration. The back-ends may be monolithic
power stages (such as the TAS5110) or six discrete differential power stages using gate drivers (such as the
the TAS55182) and MOSFETs in single-ended or bridged configurations.
The TAS5110 device is optimised for bridge tied load (BTL) configurations. These devices require a pure
differential PWM signal with a third signal (VALID) to control the MUTE state. In the MUTE state, the TAS5110
OUTA and OUTB are both low.
One Channel
of TAS5036
PWM_AP
PWM_AM
VALID
TAS5110
OUTA
OUTB
AP
AM
RESET
BP
BM
Speaker
Figure 2
–
12. PWM Outputs and H-Bridge Driven in BTL Configuration
2.5
I
2
C Serial Control Interface
The TAS5036 has a bidirectional serial control interface that is compatible with the I
2
C (Inter IC) bus protocol
and supports both 100 KBPS and 400 KBPS data transfer rates for single and multiple byte write and read
operations. This is a slave only device that does not support a multi-master bus environment or wait state
insertion. The control interface is used to program the registers of the device and to read device status.
The TAS5036 supports the standard-mode I
2
C bus operation (100 kHz maximum) and the fast I
2
C bus
operation (400 kHz maximum). The TAS5036 performs all I
2
C operations without I
2
C wait cycles.
The I
2
C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits
in a system. Data is transferred on the bus serially one bit at a time. The address and data are transferred in
byte (8 bit) format with the most significant bit (MSB) transferred first. In addition, each byte transferred on the
bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with
the master device driving a start condition on the bus and ends with the master device driving a stop condition
on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate a start and
stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in
Figure 2
–
13. The master generates the 7-bit slave address and the read/write (R/W) bit to open
communication with another device and then waits for an acknowledge condition. The TAS5036 holds SDA
low during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits
the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte).
All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. I
2
C An
external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TAS5036IPFCRG4 | 功能描述:音頻 DSP Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS5036PFC | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR |
| TAS5036PFCR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR |
| TAS5066 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIX-CHANNEL Digital Audio PWM Processor |
| TAS5066-5111D6EVM | 功能描述:音頻 IC 開發(fā)工具 TAS5066-5111D6 EVAL MOD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
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