
Introduction
5
SLES044B
—
November 2002
TAS5036
TERMINAL
NAME
DESCRIPTION
I/O
NO.
PLL_FLT_OUT
5
AO
PLL external filter
PLL_FLT_RET
6
AO
PLL external filter (internally connected to AVSS_PLL)
PWM_AM_1
74
DO
PWM 1 output (differential -); {positive H-bridge side}
PWM_AM_2
69
DO
PWM 2 output (differential -); {positive H-bridge side}
PWM_AM_3
64
DO
PWM 3 output (differential -); {positive H-bridge side}
PWM_AM_4
54
DO
PWM 4 output (differential -); {positive H-bridge side}
PWM_AM_5
49
DO
PWM 5 output (differential -); {positive H-bridge side}
PWM_AM_6
44
DO
PWM 6 output (differential -); {positive H-bridge side}
PWM_AP_1
75
DO
PWM 1 output (differential +); {positive H-bridge side}
PWM_AP_2
70
DO
PWM 2 output (differential +); {positive H-bridge side}
PWM_AP_3
65
DO
PWM 3 output (differential +); {positive H-bridge side}
PWM_AP_4
55
DO
PWM 4 output (differential +); {positive H-bridge side}
PWM_AP_5
50
DO
PWM 5 output (differential +); {positive H-bridge side}
PWM_AP_6
45
DO
PWM 6 output (differential +); {positive H-bridge side}
PWM_BM_1
72
DO
PWM 1 output (differential -); {negative H-bridge side}
PWM_BM_2
67
DO
PWM 2 output (differential -); {negative H-bridge side}
PWM_BM_3
62
DO
PWM 3 output (differential -); {negative H-bridge side}
PWM_BM_4
52
DO
PWM 4 output (differential -); {negative H-bridge side}
PWM_BM_5
47
DO
PWM 5 output (differential -); {negative H-bridge side}
PWM_BM_6
42
DO
PWM 6 output (differential -); {negative H-bridge side}
PWM_BP_1
71
DO
PWM 1 output (differential +); {negative H-bridge side}
PWM_BP_2
66
DO
PWM 2 output (differential +); {negative H-bridge side}
PWM_BP_3
61
DO
PWM 3 output (differential +); {negative H-bridge side}
PWM_BP_4
51
DO
PWM 4 output (differential +); {negative H-bridge side}
PWM_BP_5
46
DO
PWM 5 output (differential +); {negative H-bridge side}
PWM_BP_6
41
DO
PWM 6 output (differential +); {negative H-bridge side}
RESET
12
DI
System reset input, active low
I2C serial control clock input
SCL
17
DI
SCLK
30
DIO
Serial audio data clock (shift clock)
I2C serial control data input/ output
SDA
16
DIO
SDIN1
26
DI
Serial audio data 1 input
SDIN2
27
DI
Serial audio data 2 input
SDIN3
28
DI
Serial audio data 3 input
VALID_1
73
DO
Output indicating validity of PWM outputs, channel 1, active high
VALID_2
68
DO
Output indicating validity of PWM outputs, channel 2, active high
VALID_3
63
DO
Output indicating validity of PWM outputs, channel 3, active high
VALID_4
53
DO
Output indicating validity of PWM outputs, channel 4, active high
VALID_5
48
DO
Output indicating validity of PWM outputs, channel 5, active high
VALID_6
43
DO
Output indicating validity of PWM outputs, channel 6, active high
VREGA_CAP
9
P
C05 voltage regulator capacitor
VREGB_CAP
60
P
C05 voltage regulator capacitor
VREGC_CAP
34
P
C05 voltage regulator capacitor
XTL_IN
79
AI
Crystal or TTL level clock input
XTL_OUT
78
AO
Crystal output (not for external usage)