參數(shù)資料
型號: TAS5028PAGRG4
廠商: Texas Instruments, Inc.
英文描述: 8 Channel Digital Audio PWM Processor
中文描述: 8通道數(shù)字音頻PWM處理器
文件頁數(shù): 61/84頁
文件大?。?/td> 1051K
代理商: TAS5028PAGRG4
Serial Control Interface Register Definitions
53
SLES112 — June 2004
TAS5028
6
Serial Control Interface Register Definitions
Unless otherwise noted, the I
2
C register default values are in
bold
font.
Note that u indicates unused bits.
6.1
Clock Control Register (0x00)
Bit D1 is
Don’t Care
.
Table 6-1. Clock Control Register
D1
D0
-
32-kHz data rate
-
38-kHz data rate
-
44.1-kHz data rate
-
48-kHz data rate
-
88.2-kHz data rate
-
96-kHz data rate
-
176.4-kHz data rate
-
192-kHz data rate
MCLK frequency = 64
MCLK frequency = 128
MCLK frequency = 192
MCLK frequency = 256
MCLK frequency = 384
MCLK frequency = 512
MCLK frequency = 768
Reserved
1
Clock register is valid (read only)
0
Clock register is not valid (read only)
D7
0
0
0
0
1
1
1
1
-
-
-
-
-
-
-
-
-
-
D6
0
0
1
1
0
0
1
1
-
-
-
-
-
-
-
-
-
-
D5
0
1
0
1
0
1
0
1
-
-
-
-
-
-
-
-
-
-
D4
-
-
-
-
-
-
-
-
0
0
0
0
1
1
1
1
-
-
D3
-
-
-
-
-
-
-
-
0
0
1
1
0
0
1
1
-
-
D2
-
-
-
-
-
-
-
-
0
1
0
1
0
1
0
1
-
-
FUNCTION
6.2
General Status Register 0 (0x01)
Table 6-2. General Status Register (0x01)
D2
D1
D0
-
-
-
Clip indicator
-
-
-
Bank switching busy
0
0
1
Identification code for TAS5028
D7
1
-
-
D6
-
1
-
D5
-
-
0
D4
-
-
0
D3
-
-
0
FUNCTION
6.3
Error Status Register (0x02)
Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must
clear the register (write zeroes) and than read them to determine if there are any persistent errors.
Table 6-3. Error Status Register (0X02)
D1
D0
-
-
PLL phase lock error
-
-
PLL auto lock error
-
-
SCLK error
-
-
LRCLK error
-
-
Frame slip
0
0
No errors
D7
1
-
-
-
-
0
D6
-
1
-
-
-
0
D5
-
-
1
-
-
0
D4
-
-
-
1
-
0
D3
-
-
-
-
1
0
D2
-
-
-
-
-
0
FUNCTION
相關(guān)PDF資料
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