參數(shù)資料
型號： TAS5028APAGRG4
廠商： Texas Instruments, Inc.
英文描述： 8 Channel Digital Audio PWM Processor
中文描述： 8通道數(shù)字音頻PWM處理器
文件頁數(shù)： 43/82頁
文件大?。?/td> 1226K
代理商： TAS5028APAGRG4
Electrical Specifications
36
SLES120
September 2004
TAS5028A
3.4
Electrical Characteristics Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
3.3 V TTL and 5 V
(6)
tolerant
High-level output voltage
1.8-V LVCMOS (XTL_OUT)
3.3-V TTL and 5 V
(6)
tolerant
Low-level output voltage
1.8-V LVCMOS (XTL_OUT)
High-impedance output current
3.3-V TTL
3.3-V TTL
1.8-V LVCMOS (XTL_IN)
Low level input current
5 V tolerant
(5)
3.3-V TTL
1.8-V LVCMOS (XTL_IN)
High level input current
5 V tolerant
(5)
TEST CONDITIONS
I
OH
= –4 mA
I
OH
= –0.55 mA
I
OL
= 4 mA
I
OL
= 0.75 mA
MIN
2.4
1.44
TYP
MAX
UNITS
V
OH
High level output voltage
V
V
OL
Low level output voltage
0.5
0.5
±
20
±
1
±
1
±
1
±
1
±
1
±
20
V
I
OZ
μ
A
V
I
= V
IL
V
I
= V
IL
V
I
= 0 V DVDD = 3 V
V
I
= V
IH
V
I
= V
IH
V
I
= 5.5 V DVDD = 3 V
Fs = 48 kHz
Fs = 96 kHz
Fs = 192kHz
Power down
Normal
Power down
I
IL
Low-level input current
μ
A
I
IH
High-level input current
μ
A
140
150
155
Digital supply voltage DVDD
Digital supply voltage, DVDD
mA
I
DD
Input supply current
8
Analog supply voltage AVDD
Analog supply voltage, AVDD
20
2
mA
NOTES:
5. 5-V tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4.
6. 5-V tolerant outputs are SCL and SDA
3.5
PWM Operation at Recommended Operating Conditions Over 0 C to 70 C
PARAMETER
TEST CONDITIONS
32-kHz data rate
±
4%
MODE
VALUE
384
UNITS
kHz
12
×
sample rate
8
×
, 4
×
, and 2
×
sample
rates
8
×
, 4
×
, and 2
×
sample
rates
– 8
Output sample rate 1
×
8
×
oversampled
44.1-, 88.2-, 176.4-kHz data rate
±
4%
352.8
kHz
48, 96, 192 kHz data rate
±
4%
384
kHz
3.6
Switching Characteristics
3.6.1 Clock Signals Over Recommended Operating Conditions (Unless Otherwise
Noted)
3.6.1.1
PLL Input Parameters and External Filter Components
PARAMETER
Frequency, XTAL IN
Frequency, MCLK (1 / t
cyc2
)
MCLK duty cycle duty cycle
TEST CONDITIONS
MIN
TYP
13.5
MAX
UNITS
MHz
MHz
f
XTALI
f
MCLKI
Only use 13.5-MHz crystal
≤
1000 ppm
2
50
40%
50%
60%
MCLK minimum high time
≥
2-V MCLK = 49.152 MHz, Within the min
and max duty cycle constraints
5
ns
MCLK minimum low time
≤
0.8-V MCLK = 49.152 MHz,
Within the min and max duty cycle constraints
5
ns
LRCLK allowable drift before LRCLK reset
External PLL filter cap C1
External PLL filter cap C2
External PLL filter resistor R
External VRA_PLL decoupling
10
MCLKs
nF
nF
nF
SMD 0603 Y5V
SMD 0603 Y5V
SMD 0603, metal film
SMD, Y5V
100
10
200
100
See the TAS5028A example application schematic in Section 7.
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