![](http://datasheet.mmic.net.cn/370000/TAS5028A_datasheet_16735498/TAS5028A_54.png)
I
2
C Serial Control Interface (Slave Address 0x36)
47
SLES120
September 2004
TAS5028A
When the correct number of bytes has been received, the TAS5028A starts processing the data.
The procedure to perform an incremental multibyte
write operation is as follows:
1.
Start a normal I
2
C write operation by sending the device address, write bit, register subaddress, and the
first four bytes of the data to be written. At the end of that sequence, send a stop condition. At this point,
the register has been opened and accepts the remaining data that is sent by writing 4
byte blocks of data
to the append subaddress (0xFE).
2.
At a later time, one or more append data transfers are performed to incrementally transfer the remaining
number of bytes in sequential order to complete the register write operation. Each of these append
operations will be composed of the device address, write bit, append subaddress (0xFE), and four bytes
of data followed by a stop condition.
3.
The operation will be terminated due to an error condition and the data will be flushed:
a.
If a new subaddress is written to the TAS5028A before the correct number of bytes have been written.
b.
If more or fewer than 4 bytes are data written at the beginning or during any of the append operations.
c.
If a read bit is sent.
4.6
Single
Byte Read
As shown in Figure 4
4, a single
byte data read transfer begins with the master device transmitting a start
condition followed by the I
2
C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
and the read/write bit, the TAS5028A responds with an acknowledge bit. In addition, after sending the internal
memory address byte or bytes, the master device transmits another start condition followed by the TAS5028A
address and the read/write bit again. This time the read/write bit will be a 1, indicating a read transfer. After
receiving the TAS5028A and the read/write bit the TAS5028A again responds with an acknowledge bit. Next,
the TAS5028A transmits the data byte from the memory address being read. After receiving the data byte,
the master device transmits a not acknowledge followed by a stop condition to complete the single
byte
data
read transfer.
A6
A5
A0 R/W ACK A7
A6
A5
A4
A0 ACK
A6
A5
A0
ACK
Start
Condition
Stop
Condition
Acknowledge
Acknowledge
Acknowledge
I
2
C Device Address and
Read/Write Bit
Sub-Address
Data Byte
D7
D6
D1
D0 ACK
I
2
C Device Address and
Read/Write Bit
Not
Acknowledge
R/W
A1
A1
Repeat Start
Condition
Figure 4
4. Single
Byte Read Transfer
4.7
Multiple
Byte Read
A multiple
byte data
read transfer is identical to a single
byte data read transfer except that multiple data
bytes are transmitted by the TAS5028A to the master device as shown in Figure 4
5. Except for the last data
byte, the master device responds with an acknowledge bit after receiving each data byte.
A6
A0
ACK
Acknowledge
I
2
C Device Address and
Read/Write Bit
R/W
A6
A0 R/W ACK
A0
ACK
D7
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
Acknowledge
Acknowledge
Last Data Byte
ACK
First Data Byte
Repeat Start
Condition
Not
Acknowledge
I
2
C Device Address and
Read/Write Bit
Sub-Address
Other Data Bytes
A7
A6
A5
D7
D0 ACK
Acknowledge
D7
D0
Figure 4
5. Multiple Byte Read Transfer