參數(shù)資料
型號(hào)： TAS5026PAGR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 10/52頁(yè)
文件大?。?/td> 886K
代理商： TAS5026PAGR
Architecture Overview
13
SLES041B—November 2002
TAS5026
22
21
SCLK
24 Clks
LRCLK
Left Channel
19
9
8
1
0
MSB
LSB
2-Channel Left-Justified Stereo Input/Output (24-Bit Transfer Word Size)
3
2
4
20
23
22
21
24 Clks
Right Channel
19
9
8
1
0
MSB
LSB
3
2
4
20
23
5
24-Bit Mode
Figure 2–6. Left-Justified 48-Fs Format
2.1.7.3
Right-Justified Timing
Right-justified (RJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and
when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock
running at 48 or 64 times Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock
periods (for 24-bit data) after LRCLK toggles. In RJ mode, the last bit clock before LRCLK transitions always
clocks the LSB of data. The data is written MSB first and is valid on the rising edge of bit clock. The TAS5026
masks unused leading data bit positions. Master mode only supports a 64 times Fs bit clock.
23
22
SCLK
32 Clks
LRCLK
Left Channel
24-Bit Mode
19
18
15
14
1
0
19
18
20-Bit Mode
15
14
1
0
16-Bit Mode
1
0
15
14
MSB
LSB
2-Channel Right-Justified (Sony Format) Stereo Input
NOTE: All data presented in 2s complement form with MSB first.
23
22
32 Clks
Right Channel
19
18
15
14
1
0
19
18
15
14
1
0
1
0
15
14
MSB
LSB
Figure 2–7. Right-Justified 64-Fs Format
相關(guān)PDF資料
PDF描述
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TAS5028 制造商:TI 制造商全稱:Texas Instruments 功能描述:8 Channel Digital Audio PWM Processor
TAS5028-5122C6EVM 功能描述:音頻 IC 開發(fā)工具 TAS5028-5122C6 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
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