參數(shù)資料
型號: TAS5026IPAG
廠商: Texas Instruments, Inc.
英文描述: SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR
中文描述: 六聲道數(shù)字音頻PWM處理器
文件頁數(shù): 29/48頁
文件大小: 689K
代理商: TAS5026IPAG
Serial Control Interface Register Definitions
24
SLES041B
November 2002
TAS5026
3
Serial Control Interface Register Definitions
Table 3
1 shows the register map for the TAS5026. Default values in this section are in bold.
Table 3
1. I
2
C Register Map
ADDR HEX
DESCRIPTION
00
General status register
01
Error status register
02
System control register 0
03
System control register 1
04
Error recovery register
05
Automute delay
06
DC-offset control register channel 1
07
DC-offset control register channel 2
08
DC-offset control register channel 3
09
DC-offset control register channel 4
0A
DC-offset control register channel 5
0B
DC-offset control register channel 6
0C
Interchannel delay register channel 1
0D
Interchannel delay register channel 2
0E
Interchannel delay register channel 3
0F
Interchannel delay register channel 4
10
Interchannel delay register channel 5
11
Interchannel delay register channel 6
12
Reserved
13
Volume control register channel 1
14
Volume control register channel 2
15
Volume control register channel 3
16
Volume control register channel 4
17
Volume control register channel 5
18
Volume control register channel 6
19
Individual channel mute
The volume table is contained in Appendix A.
Default values are shown in bold in the following tables
NOTE:
The performance of a TDAA system is optimized by setting the PWM timing based upon the
type of back-end device that is used and, to a lesser extent, the layout. These values are set
during initialization using the I
2
C serial interface. The specific timing parameter values for each
PWM and back-end configuration is contained in the EVM User Manual, Reference Design
User Manual, and design application note for these devices. Please refer to the appropriate
EVM User Manual, Reference Design user manual, or design application note for these
values.
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