參數(shù)資料
型號(hào): TAS5026APAG
廠商: Texas Instruments, Inc.
英文描述: Six-Channel Digital Audio PWM Processor
中文描述: 六聲道數(shù)字音頻PWM處理器
文件頁(yè)數(shù): 18/62頁(yè)
文件大?。?/td> 769K
代理商: TAS5026APAG
Architecture Overview
12
SLES068A—February 2003—Revised January 2004
TAS5026A
2.1.7.1
I
2
S Timing
I
2
S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for
the right channel. The LRCLK is low for the left channel and high for the right channel. A bit clock running at
48 or 64 times Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal
changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising
edge of the bit clock. The TAS5026A masks unused trailing data bit positions. Master mode only supports a
64 times Fs bit clock.
23
22
SCLK
32 Clks
LRCLK (Note Reversed Phase)
Left Channel
24-Bit Mode
9
8
5
4
1
0
19
18
20-Bit Mode
5
4
1
0
16-Bit Mode
1
0
15
14
MSB
LSB
23
22
SCLK
32 Clks
Right Channel
9
8
5
4
1
0
19
18
5
4
1
0
1
0
15
14
MSB
LSB
2-Channel I2S (Philips Format) Stereo Input
Figure 23. I
2
S 64-Fs Format
2-Channel I2S Stereo Input/Output (24-Bit Transfer Word Size)
23
22
SCLK
24 Clks
LRCLK
Left Channel
24-Bit Mode
20
19
8
7
2
1
19
18
20-Bit Mode
16
15
1
0
16-Bit Mode
1
0
15
14
MSB
LSB
4
3
5
21
4
5
17
13
12
11
23
22
SCLK
24 Clks
Right Channel
20
19
8
7
2
1
19
18
16
15
1
0
1
0
15
14
MSB
LSB
4
3
5
21
4
5
17
13
12
11
0
Figure 24. I
2
S 48-Fs Format
相關(guān)PDF資料
PDF描述
TAS5026APAGRG4 Six-Channel Digital Audio PWM Processor
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TAS5026APAGRG4 功能描述:音頻 DSP 6Ch Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS5026CPAG 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR
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