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參數(shù)資料
| 型號： | TAS5015PFBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 266K |
| 代理商： | TAS5015PFBR |
TAS5015
SLES017 SEPTEMBER 2001
8
www.ti.com
functional description (continued)
Initialization
Chip
Power-Down
PDN and RESET
Normal Operation
Normal
Operation
VALID
Figure 4. Power-Down Timing
mute
The TAS5015 provides a mute function that is used when the MUTE pin is asserted low. See Table 2 for mute
description. This mute is a quiet mute; that is, the mute is accomplished by outputting a zero value waveform
in which both sides of the differential PWM outputs have a 50% duty cycle (see Figure 5 for mute timing).
Table 2. Mute Description
MUTE
P OUTPUTS
M OUTPUTS
DESCRIPTION
0
50% duty cycle
Mute
1
DATA
Normal operation
Initialization
Normal State
MUTE
VALID_L
5 ms max
10
s max
5050 Duty Cycle
(P, M Complementary)
Inactive State
VALID_R
PWM Outputs
(P, M Complementary)
Figure 5. Mute Timing
double speed
Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz. In order to put the TAS5015 in
double-speed mode with the device in normal operating conditions, the RESET pin must be held low while
switching the DBSPD pin high. After the RESET pin is brought high again, a reset sequence takes place. If the
change is at power up, a power-up sequence is originated.
quad speed
Quad-speed mode is used to support sampling rates of 176.4 kHz and 192 kHz. In order to put the TAS5015
in quad-speed slave mode, M_S and DBPSB pins are brought low. Quad-speed mode is then automatically
detected due to the fact that it is the only mode in which MCLK_IN is 128 Fs. DEM_SEL must be set to low when
operating in the quad-speed slave mode. For quad-speed master mode M_S = 1, DBSPD = 0, DEM_SEL = 1,
and DEM_EN = 0.
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