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參數(shù)資料
| 型號(hào)： | TAS5015PFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 266K |
| 代理商： | TAS5015PFBG4 |
TAS5015
SLES017 SEPTEMBER 2001
10
www.ti.com
functional description (continued)
Table 4. Hardware Selection of Serial Audio Modes
MODE
MOD2 PIN
MOD1 PIN
MOD0 PIN
SERIAL INTERFACE
SDIN
0
16-bit, MSB first; right justified
1
0
1
20-bit, MSB first; right justified
2
0
1
0
24-bit, MSB first; right justified
3
0
1
16-bit IIS
4
1
0
20-bit IIS
5
1
0
1
24-bit IIS
6
1
0
16-bit MSB first, left justified
7
1
16-bit DSP frame
The following figures illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the
different interface protocols. Note that there are always 64 SCLKs per LRCLK. The nondata bits are padded
with binary 0s.
MSB first, right-justified (for 16, 20, 24 bits)
X
MSB
LSB
MSB
LSB
SCLK
LRCLK = fs
SDIN
Left Channel
Right Channel
X
Figure 7. MSB First Right Justified
Note the following characteristics of this protocol.
Left channel is received when LRCLK is high.
Right channel is received when LRCLK is low.
SDIN is sampled at the rising edge of SCLK.
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