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參數(shù)資料
| 型號： | TAPC640 |
| 廠商： | Lineage Power |
| 英文描述： | High-Speed Switching ATM Port Controller (APC)(高速開關(guān)ATM端口控制器) |
| 中文描述： | 高速開關(guān)ATM端口控制器（APC）（高速開關(guān)自動柜員機(jī)端口控制器） |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 165K |
| 代理商： | TAPC640 |
Product Brief
August 2000
TAPC640
High-Speed Switching ATM Port Controller (APC)
5
Lucent Technologies Inc.
Description
(continued)
Buffer Management Controller (BMX)
(continued)
The buffer is logically partitioned so that each traffic
class can support a different buffer reservation inde-
pendent of other classes. Additional mechanisms are
provided to control the sharing of buffers between ports
with minimum guarantees for each port.
An optional partial packet discard (PPD) mode is sup-
ported for each connection. A static selective explicit
forward congestion indicator (SEFCI) marking thresh-
old is also provided. EFCI marking can be selectively
enabled for each connection.
Cell Buffer Memory Interface (BRI)
The BRI handles all the necessary operations needed
to read, write, and refresh the cell data in ingress and
egress cell buffer pools maintained in external SDRAM
(BRAM). The BRI supports up to 512K cell buffers
which can be statically partitioned between ingress and
egress without restriction. The BRI performs cell
enqueue and dequeue operations and serves also as
intermediate cell storage to support NMXSOX and
XREAFE operations.
Additionally, the BRI manages the communication
between the APC and the ingress and egress cell
pointer memory maintained in external SDRAM
(PRAM).
Ingress Queue Scheduler (iQSC)
The iQSC implements a sophisticated per virtual con-
nection queue architecture and hierarchical scheduling
algorithms for ingress.
The iQSC performs the virtual connection enqueue and
dequeue operations, which are supported by the HLX,
VCT, and BRI blocks.
The iQSC provides novel scheduling algorithms to ser-
vice up to 64K VC queues and five traffic classes
(CBR, rt-VBR, nrt-VBR, ABR, and UBR) using a three-
level hierarchy. The first (VC) level of the hierarchy con-
tains per-VC schedulers for each of the five traffic
classes. Each VC scheduler can support all 64K VC
queues as needed. The second (class) level of the hier-
archy contains two class schedulers: one to provide
guaranteed bandwidth and one to distribute excess
bandwidth to each work-conserving VC scheduler. The
third (port merge) level of the hierarchy merges the
CBR VC scheduler and the two class schedulers
together.
The CBR scheduler uses a non-work-conserving
shaped virtual clock (ShVC) algorithm to shape CBR
virtual connections to any one of up to 32 user-
programmable rates.
The rt-VBR scheduler uses a work-conserving starting
potential fair queuing (SPFQ) algorithm to schedule vir-
tual connections using any one of up to 16 user-
programmable rates/weights.
nrt-VBR, ABR, and UBR schedulers each use a work-
conserving variable length frame based weighted
round-robin (WRR) algorithm to schedule virtual con-
nections using one of up to 256K different weights.
The guaranteed traffic class scheduler (GTS) uses the
ShVC algorithm to provide guaranteed bandwidth to
each of four classes (the rt-VBR, nrt-VBR, ABR, and
UBR VC schedulers). A user-programmable rate is pro-
vided for each class.
The excess bandwidth class scheduler (EBS) uses a
work-conserving self-clocked fair queuing (SCFQ)
algorithm to fairly allocate excess bandwidth to each of
four classes (the rt-VBR, nrt-VBR, ABR, and UBR VC
schedulers). A user-programmable weight is provided
for each class.
The port merge scheduler merges the CBR VC sched-
uler and the GTS class scheduler together with strict
priority over the EBS class scheduler. CBR and GTS
service is arbitrated at this level using timestamps.
Switch Fabric Interface (SXI)
The SXI implements an interface to ATLANTA switch
fabrics, as well as a loopback mode for a single APC
stand-alone operation. The SXI interface consists of an
8-bit parallel data bus plus additional control signals
and clock, operating at up to 100 MHz. The SXI termi-
nates the simple ATLANTA abric interface protocol.
The transmit interface can be configured to generate
odd or even parity. The receive interface checks for odd
parity and protocol violations. It also extracts the fabric
backpressure information from the cell header.
This interface is duplicated to allow construction of
redundant switch fabric architectures for fault tolerance,
and 1.2 Gbits/s fabric-less switches using two APCs.
Each transmit interface can be independently enabled
and disabled.
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