參數(shù)資料
型號(hào)： TA1370FG
元件分類： 信號(hào)分離
英文描述： SYNC SEPARATOR IC, PDSO30
封裝： 0.375 INCH, 1 MM PITCH, PLASTIC, SSOP-30
文件頁數(shù)： 6/42頁
文件大?。?/td> 902K
代理商： TA1370FG
TA1370FG
2005-09-05
14
TEST (Test mode)
Switches DAC1, 2, and 3 outputs. Also used to test IC for shipping.
*(0): DAC outputs are used as DAC.
(1): DAC1 outputs V. SYNC to the frequency counter.
DAC2 outputs H. SYNC or C. SYNC to the frequency counter.
DAC3 outputs IC test pulse for shipping.
HD1-INV (HD1 output polarity switch)
Switches HD1 output (pin 16) polarity. When set to 0, positive HD input is output as negative HD. When
set to 0, output from the sync circuit is output as negative HD.
*(0): Normal
(1): Inverse
HD2-INV (HD2 output polarity switch)
Switches HD1 output (pin 19) polarity. When set to 0, positive HD input is output as negative HD. When
set to 0, output from the sync circuit is output as negative HD.
*(0): Normal
(1): Inverse
V-FREQUENCY (Vertical frequency switch (pull-in range))
Sets vertical frequency pull-in range, VD-STOP, or free-running frequency.
Free-running frequency is controlled by H-FREQUENCY.
Pull-in Range
Format/H (V) Frequency
*(000)
48~849 H
750P/60 Hz (45 kHz)
(001)
48~725 H
625P/50 Hz (31.25 kHz)
(010)
FREE-RUN
Free-running frequency is controlled by H-FREQUENCY.
(00): 562 H
(01): 525 H
(10): 562 H
(11): 750 H
(011)
48~637 H
1125I/60 Hz (33.75 kHz), 1125I/50Hz (28.125 kHz)
(100)
48~613 H
525P/60 Hz (31.5 kHz)
(101)
48~363 H
PAL/SECAM double scan/100 Hz (31.5 kHz)
(110)
48~307 H
NTSC double scan /120 Hz (31.5 kHz)
(111)
VD STOP
VD output is HIGH
CLP PHS (Clamp pulse phase switch)
Switches clamp pulse phase.
If no signal input, 0.9
s pulse is output from the H-C/D circuit.
*(0): 1
s (3.4%) delay following HD stop phase, 0.8 s (2.7%) pulse
(1): 0.5
s (1.7%) delay following HD stop phase, 0.8 s (2.7%) pulse
FREQ DET SW (Horizontal/vertical frequency counter switch)
Switches input signal used for horizontal/vertical frequency counter. This switch is controlled
independently from INPUT SW. The detection result is output as read BUS data.
*(00): SYNC1 input (01): SYNC2 input (10)/(11): HD3/VD3 inputs
INPUT SW (Input signal switch for synchronization)
Switches input signal used for synchronization.
*(00): SYNC1 input (01): SYNC2 input
(10)/(11): HD3/VD3 inputs
HD PHASE (HD phase adjustment)
Adjusts phase of HD output from the sync circuit. The phase of the adjustment center value is the same
as that of input H-SYNC or input HD. (Note) Synchronized VD width will change, when HD PHASE will
be changed.
(000000) :
5% (H periodically)
*(100000) :
0%
(111111) :
5%
VD1-INV (VD1 output polarity switch)
Switches VD1 output (pin 28) polarity. When set to 0, negative VD input is output as negative VD. When
set to 0, output from the sync circuit is output as negative VD.
*(0): Normal
(1): Inverse
VD2-INV (VD2 output polarity switch)
Switches VD2 output (pin 29) polarity. When set to 0, negative VD input is output as negative VD. When
set to 0, output from the sync circuit is output as negative VD.
*(0): Normal
(1): Inverse
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