參數(shù)資料
型號: TA1360AFG
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝: 14 X 20 MM, 0.80 MM HEIGHT, PLASTIC, QFP-80
文件頁數(shù): 27/110頁
文件大小: 1614K
代理商: TA1360AFG
TA1360AFG
2005-08-18
23
Data Transmit Format 1
Data Transmit Format 2
Data Receive Format
To receive data, the master transmitter changes to a receiver immediately after the first acknowledgement. The
slave receiver changes to a transmitter.
The stop condition is always created by the master.
Optional Data Transmit Format
In this way, sub addresses are automatically incremented from the specified sub address and data are set.
I
2C BUS Conditions
Characteristics
Symbol
Min
Typ.
Max
Unit
Low level input voltage
VIL
0
1.0
V
High level input voltage
VIH
1.8
Vcc
V
Low level output voltage at 3 mA sink current
VOL1
0
0.4
V
Input current each I/O pin with an input voltage
between 0.1 VDD and 0.9 VDD
Ii
10
10
A
Capacitance for each I/O pin
Ci
10
pF
SCL clock frequency
fSCL
0
100
kHz
Hold time START condition
tHD;STA
4.0
s
Low period of SCL clock
tLOW
4.7
s
High period of SCL clock
tHIGH
4.0
s
Set-up time for a repeated START condition
tSU;STA
4.7
s
Data hold time
tHD;DAT
350
ns
Data set-up time
tSU;DAT
250
ns
Set-up time for STOP condition
tSU;STO
4.0
s
Bus free time between a STOP and START condition
tBUF
4.7
s
S
Slave address
0 A
Transmit data 1
A
Sub address
A
Transmit data n
A
Sub address
A P
S
Slave address
1 A
A
Receive data
P
7 bit
MSB
8 bit
MSB
S
Slave address
A
Transmit data n
Transmit data 1
A P
7 bit
MSB
8 bit
MSB
0
Sub address
7 bit
MSB
A 1
8 bit
MSB
S
Slave address
0 A
Transmit data
A
Sub address
A P
7 bit
MSB
S: Start condition
8 bit
MSB
A: Acknowledgement
9 bit
MSB
P: Stop condition
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