參數(shù)資料
型號(hào): T89C5115-RATIM
廠商: Atmel
文件頁數(shù): 82/113頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 16K 32VQFP
標(biāo)準(zhǔn)包裝: 250
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-LQFP
包裝: 托盤
其它名稱: T89C5115-RASIM
T89C5115-RASIM-ND
dsPIC33FJ12MC201/202
DS70265E-page 70
2007-2011 Microchip Technology Inc.
6.9.1
ILLEGAL OPCODE RESET
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The illegal opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the illegal opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bits should be programmed with 3Fh,
which is an illegal opcode value.
6.9.2
UNINITIALIZED W REGISTER
RESET
Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
Resets and is considered uninitialized until written to.
6.9.3
SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
The VFC occurs when the Program Counter is
reloaded with an Interrupt or Trap vector.
for more information on
Security Reset.
6.10
Using the RCON Status Bits
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the Reset.
Table 6-3 provides a summary of Reset flag bit
operation.
TABLE 6-3:
RESET FLAG BIT OPERATION
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
Flag Bit
Set by:
Cleared by:
TRAPR (RCON<15>)
Trap conflict event
POR, BOR
IOPWR (RCON<14>)
Illegal opcode or uninitialized
W register access or Security Reset
POR, BOR
CM (RCON<9>)
Configuration Mismatch
POR, BOR
EXTR (RCON<7>)
MCLR Reset
POR
SWR (RCON<6>)
RESET
instruction
POR, BOR
WDTO (RCON<4>)
WDT Time-out
PWRSAV
instruction,
CLRWDT
instruction, POR, BOR
SLEEP (RCON<3>)
PWRSAV #SLEEP
instruction
POR, BOR
IDLE (RCON<2>)
PWRSAV #IDLE
instruction
POR, BOR
BOR (RCON<1>)
POR, BOR
POR (RCON<0>)
POR
Note:
All Reset flag bits can be set or cleared by user software.
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