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參數(shù)資料
| 型號： | T8534 |
| 英文描述： | T8533/34 Quad Programmable Line Card Signal Processor |
| 中文描述： | T8533/34四線卡可編程信號處理器 |
| 文件頁數(shù)： | 43/48頁 |
| 文件大?。?/td> | 890K |
| 代理商： | T8534 |
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Preliminary Data Sheet
July 2001
Signal Processor
T8533/34 Quad Programmable Line Card
Agere Systems Inc.
43
Software Interface
(continued)
Table 18. Control Bit Definitions
(continued)
Control Name
(Address, Decimal)
[Address, Hex]
ZEQCTRL
(150—152)
[0x96—0x98]
GTX1
(153—154)
[0x99—0x9a]
TXBITOFF
(155)
[0x9b]
Bit
Assignments
Function
0—20
Coefficients for the equalization stage that accommodates current-sens-
ing SLICs. Defaults to 0x000000.
0—11
Gain control for tweak gain stage in transmit direction. Defaults to 0x051a
(2.11 dB). This is a 12-bit multiply operation with a maximum gain of 4
(12 dB).
Transmit direction bit offset for the FS signal. Defaults to 0. These 3 bits
can be thought of as the least significant bits (TXOFF contains the more
significant bits) of a bit counter that determines the location of the first bit
of the PCM data from FS.
Load as 0.
Transmit time-slot assignment. Defaults to (16 * channel number). Each
time slot represents 8 bits, allow for two time slots when using linear
mode.
3-state transmit PCM interface. Defaults to 0. A 1 forces the PCM inter-
face into a high-impedance state during its assigned time slot on the PCM
bus. Placing the channel in standby mode also forces a high-impedance
condition on the transmit interface.
Transmit zeroes instead of data. Defaults to 0 (off).
Load as 0.
Place idle channel code on receive path. Defaults to 0 (off).
Loopback receive to transmit at PCM conversion interface (
digital loop-
back 1
). Defaults to 0 (no loopback).
Loopback transmit to receive at PCM conversion interface (
digital loop-
back 4
). Defaults to 0 (no loopback).
Linear/companded. A 1 sets 16-bit linear mode with two adjacent time
slots used, LSB transmitted first. Linear data is in two’s complement form.
A 0 sets companded mode with only one time slot used, and MSB trans-
mitted first. Defaults to 0.
μ
-law or A-law. A 0 sets
μ
-law mode, and a 1 sets A-law mode. This bit
has no effect if bit 1 of this address is set to 1. Defaults to 0 (
μ
-law).
Load as 0.
Controls the drivers for the corresponding SLIC latches. A 1 enables the
pin as an output. Defaults to 0x0c (bits 2 and 3 set, the rest cleared).
Load as 0.
SLIC data latches. If the corresponding bit in the SLICTS address is set
for an output, the device will drive the corresponding bit according to the
contents of this address. Writes are performed within 125
μ
s. Wait
125
μ
s before a subsequent write to the same channel or between
write
all channel
commands. Default is 0.
Not used, ignore on a codec read command addressing this location.
Reports the actual state of the SLIC pins. Anything written to this address
is ignored. Updates within 125
μ
s.
Test location for serial interface. This location has no internal use, but
merely latches write data for the purpose of testing the serial interface.
This register does not clear with reset.
This bit is set to a 1 if a data call is in progress. Do not attempt to write this
register.
Internal state control bits; do not write and ignore on read.
5—7
0—4
0—7
TXOFF
(156)
[0x9c]
PCMCTRL
(157)
[0x9d]
7
6
5
4
3
2
1
0
SLICTS
(158)
[0x9e]
6—7
0—5
SLICWR
(159)
[0x9f]
6—7
0—5
SLICRD
(160)
[0xa0]
6—7
0—5
VERIFY
(162)
[0xa2]
DATACALL
(167)
[0xa7]
0—7
5
0—4, 6, 7
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