
TE
CH
tm
MEASUREMENT CIRCUITS 
                                                                     T63H0008A
TM Technology, Inc. reserves the right 
P. 6                                    
Publication Date: Dec. 2003 
to change products or specifications without notice.                                                                          Revision:A 
Unless otherwise specified, the output voltage levels “H” and “L” at COUT and DOUT pins are judged by the 
threshold voltage (1.0V) of the N channel FET. Judge the COUT pin level with respect to V- and the DOUT pin 
level with respect to VSS. 
(1) Measurement Condition 1, Measurement Circuit 1 
(Overcharge detection voltage, Overcharge hysteresis voltage).       
The overcharge detection voltage (VDET1) is defined by the voltage between VDD and VSS at which VCO 
goes “L” from “H” when the voltage V1 is gradually increased from the starting condition V1=3.5V and 
V2=0V. The overcharge hysteresis voltage (VHCT1) is then defined by the difference between the 
overcharge detection voltage (VDD) and the voltage between VDD and VSS at which VCOUT goes “H” 
from “L” when the voltage V1 is gradually decreased. 
(2) Measurement Condition 2, Measurement Circuit 2 
(Over-discharge detection voltage, Over-discharge hysteresis voltage)      
The over-discharge detection voltage (VDET2) is defined by the voltage between VDD and VSS at   which 
VDO goes “L” from “H” when the voltage V1 is gradually decreased from the starting condition V1=3.5V 
and V2=0V. The over-discharge hysteresis voltage (VHDT2 ) is then defined by the difference between the 
over-discharge detection voltage (VDET2) and the voltage between VDD and VSS at which VDO goes 
“H” from “L” when the voltage V1 is gradually increased. 
(3) Measurement Condition 3, Measurement Circuit 2 
(Over-current 1 detection voltage, Over-current 2 detection voltage, Load short-circuiting detection voltage) 
The over-current 1 detection voltage is defined by the voltage between V- and VSS whose delay time for 
changing VDO from “H” to “L” lies between the minimum and the maximum value of the over-current 1 
detection delay time when the voltage V2 is increased rapidly within 10us from the starting condition 
V1=3.5V and V2=0V.  
The over-current 2 detection voltage is defined by the voltage between V- and VSS whose delay time for 
changing VDO from “H” to “L” lies between the minimum and the maximum value of the over-current 2 
detection delay time when the voltage V2 is increased rapidly within 10us from the starting condition 
V1=3.5V and V2=0V. 
The load short-circuiting detection voltage is defined by the voltage between V- and VSS whose delay time 
for changing VDO from “H” to “L” lies between the minimum and the maximum value of the load 
short-circuiting detection delay time when the voltage V2 is increased rapidly within 10us from the starting 
condition V1=3.5V and V2=0V.