
TE
CH
tm
T431616D/E
TM Technology Inc. reserves the right
P. 14
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
A8
0
0
1
A7
0
1
X
Test Mode
normal mode
Vendor Use Only
Vendor Use Only
Single Write Mode (A9)
This bit is used to select the write mode. When the BS bit is "0", the Burst-Read-Burst-Write mode is
selected. When the BS bit is "1", the Burst-Read-Single-Write mode is selected.
A9
0
1
Single Write Mode
Burst-Read-Burst-Write
Burst-Read-Single-Write
Note: A10 and A11 should stay “L” during mode set cycle.
8
No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
This prevents unwanted commands from being registered during idle or wait states.
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low).
9
Burst Stop command
(RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is only
effective in a read/write burst without the auto precharge function. The terminated read burst ends after a delay
equal to the CAS# latency (refer to the following figure). The termination of a write burst is shown in the
following figure.
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Burst Stop
DOUT A0
DOUT A1
DOUT A2
DOUT A3
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
The burst ends after a delay equal to the CAS# latency.
Termination of a Burst Read Operation
(Burst Length
4, CAS# Latency = 1, 2, 3)