參數(shù)資料
型號: T4260ILS
廠商: ATMEL CORP
元件分類: 調(diào)諧器
英文描述: AUDIO TUNER, PDSO44
封裝: SSO-44
文件頁數(shù): 8/30頁
文件大小: 299K
代理商: T4260ILS
16
T4260
4528I–AUDR–08/04
If bits 20 and 21 (HCDEL 1) or bits 22 and 23 (HDCEL 2) are both set to 0, then the
high-current charge pump is deactivated. Otherwise, the delay time can be selected as
described in Table 13.
2-bit Shift
A divider 2-bit shift (bit 32 = 0) allows faster frequency changes by using a four times
higher step frequency (e.g., f
PDF = 50 kHz instead of fPDF = 12.5 kHz). If the PLL is
locked (after the frequency change), the normal step frequency (e.g., f
PDF = 12.5 kHz)
will be active again.
If no 2-bit shift is used (bit 32 = 1), the frequency changes will be done with the normal
step frequency (12.5 kHz).
In 2-bit shift mode the N- and R-divider are shifted by two bits to the right (this corre-
sponds by a R- and N-divider division by 4). An important condition for this mode is that
the R-divider has to be a multiple of 4.
SW1 (Pin 13)
The switching output SW1 (pin 13) is controlled by bit 46 as given in Table 15.
Note:
SW1 is an open-drain output.
Figure 5. Internal Components at SW1
Table 13. Delay Time of HCDEL Register
High-current Charge Pump
B21/B23
B20/B22
OFF
0
Delay time 5 ns
0
1
Delay time 10 ns
1
0
Delay time 15 ns
1
Table 14. Manual and Lock Detect Shift Mode
2-bit Shift
B32
Dividers 2-bit shift
0
No shift
1
Table 15. Switching Output
SW1
B46
High
0
Low
1
SW1
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