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參數(shù)資料
| 型號： | T35L6464A-5Q |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 64K x 64 SRAM |
| 中文描述： | 64K的× 64的SRAM |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 160K |
| 代理商： | T35L6464A-5Q |
TE
CH
tm
READ TIMING
T35L6464A
Taiwan Memory Technology, Inc. reserves the right
P. 12
to change products or specifications without notice.
Publication Date: AUG. 1998
Revision: E
High-Z
BUR ST READ
C L K
A D S C
A D S P
A D D R E S S
G W , B W E ,
B W 1 - B W 8
t KC
t K H
t KL
t ADSSt ADSH
DON'T CARE
UNDEFINED
t A DSS
t ADSH
t ASt A H
t WS
t WH
t C ESt CEH
t AAS
t AA H
t OEQ
tOELZ
t KQX
tOEHZ
t KQ
t KQHZ
t KQ
t K QLZ
Single READ
(NOTE3)
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2+1)
Burst wraps around
to its inital s tate.
ADV suspends burst.
Burst c ontinued with
new base address.
Q(A2)
A 3
A 2
A1
(NOTE1)
Deselect c ycle.
C E
( N O T E 2 )
A D V
O E
Q
(NOTE4)
Note:
1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2.
CE2
, CE2,
CE3
and CE3 have timing identical to
CE
. On this diagram, when
CE
is LOW,
CE2 ,
CE3
is LOW and CE2 , CE3 is HIGH. When
CE
is HIGH,
CE2
,
CE3
is HIGH and
CE2 , CE3 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
OE
does not cause Q to be driven until after the following clock rising edge.
4. Outputs are disabled within one clock cycle after deselect.
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