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參數資料
| 型號： | T35L6432A |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 64K x 32 SRAM |
| 中文描述： | 64K的× 32的SRAM |
| 文件頁數： | 13/15頁 |
| 文件大?。?/td> | 1347K |
| 代理商： | T35L6432A |
TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right
P. 13
to change products or specifications without notice.
Publication Date: DEC. 1998
Revision:A
READ/WRITE TIMING
A4
High -Z
BUR ST R EAD
C L K
ADS C
A DS P
A DDR E S S
B W E
B W 1 - B W 4
t K C
t K H
t K L
t ADSS
t ADSH
DON'T CARE
UNDEFINED
t AS
t AH
t WS
t WH
t C E St C EH
t DH
t K Q
tOELZ
tOE HZ
t DS
t KQ
t K QLZ
Sing le W RIT E
Q(A1)
Q(A2)
Q(A3 )
Q(A4)
Q(A4+1)
Q(A4+3)
Q(A4+2)
A5
A3
A1
(NOT E1)
C E
( N O T E 2 )
ADV
O E
D
A2
A6
Q
Hig h-Z
D(A3)
D(A5)
D(A6)
Back-t o-Back READs
Pass-thr ough
R EAD
Back-to-Back
WRIT Es
Note:
1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst
address following A4.
2. CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW
and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP, ADSC or ADV
cycle is performed.
4. GW is HIGH.
5. Back-to-back READs may be controlled by either ADSP or ADSC.
相關PDF資料 |
PDF描述 |
|---|---|
| T35L6432A-5Q | 64K x 32 SRAM |
| T35L6432A-5T | 64K x 32 SRAM |
| T35L6432B | 64K x 32 SRAM |
| T35L6432B-10Q | 64K x 32 SRAM |
| T35L6432B-12T | 64K x 32 SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| T35L6432A-5Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432A-5T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B-10Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B-12T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
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