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參數(shù)資料
| 型號： | T15M1024A-70HI |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 128K X 8 LOW POWER CMOS STATIC RAM |
| 中文描述： | 128K的× 8低功耗CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 85K |
| 代理商： | T15M1024A-70HI |
TE
CH
tm
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
T15M1024A
TM Technology Inc. reserves the right
P. 7
to change products or specifications without notice.
Publication Date: FEB. 2002
Revision:A
READ CYCLE 2
(Chip Enable Controlled)
Notes (READ CYCLE) :
1.
WE
are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition referenced to
V
OH
or V
OL
levels.
4. At any given temperature and voltage condition. t
HZ
(max.) is less than t
LZ
(min.) both for a given device
and from device to device interconnection.
5. Transition is measured
±
200mV from steady state voltage with load. This parameter is sampled and not
100% tested.
6. Device is continuously selected with
1
CE
=V
IL
.
DON'T CARE
UNDEFINED
C E 1
t
OLZ
C E 2
t
ACE
t
OHZ
D
OUT
tRC
Ad d re s s
tOH
tAA
DOUT
Previous Data Valid
Data Valid
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| T15M1024A | 128K X 8 LOW POWER CMOS STATIC RAM |
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| T15M1024A-100NI | 128K X 8 LOW POWER CMOS STATIC RAM |
| T15M1024A-100P | 128K X 8 LOW POWER CMOS STATIC RAM |
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| T15M256A-70D | 制造商:TMT 制造商全稱:TMT 功能描述:32K X 8 LOW POWER CMOS STATIC RAM |
| T15M256A-70P | 制造商:TMT 制造商全稱:TMT 功能描述:32K X 8 LOW POWER CMOS STATIC RAM |
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