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參數(shù)資料
| 型號： | T14M256A |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 32K X 8 HIGH SPEED CMOS STATIC RAM |
| 中文描述： | 32K的乘八高速CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 74K |
| 代理商： | T14M256A |
TE
CH
tm
AC CHARACTERISTICS
(
Vcc
=5V
±
5%, Vss = 0V, Ta = 0 to 70
°
C)
(1) READ CYCLE
T14M256A
Taiwan Memory Technology, Inc. reserves the right
P. 4
to change products or specifications without notice.
Publication Date: SEP. 2001
Revision: G
-7
-8
-10
-12
-15
PARAMETER
SYM.
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
7
-
8
-
10
UNIT
Read Cycle Time
t
RC
t
AA
t
ACS
t
AOE
t
CLZ*
t
OLZ
0
-
12
-
15
-
ns
Address Access Time
-
7
-
8
-
10
-
12
-
15
ns
Chip Select Access Time
-
7
-
8
-
10
-
12
-
15
ns
Output Enable to Output Valid
-
3.5
-
5
-
6
-
7
-
7
ns
Chip Selection to Output in Low Z
2
-
3
-
3
-
3
-
3
-
ns
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
t
CHZ*
Output Disable to Output in High Z
-
0
-
0
-
0
-
0
-
ns
-
3.5
-
4
-
5
-
6
0
7
ns
t
OHZ
t
OH
-
3.5
-
4
-
5
-
6
0
7
ns
Output Hold from Address Change
2
-
2.5
-
3
-
3
-
3
-
ns
* These parameters are sampled but not 100% tested.
(2)WRITE CYCLE
-7
-8
-10
-12
-15
PARAMETER
SYM.
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
7
-
8
10
5
-
6
-
8
5
-
6
8
0
-
0
-
0
5
-
6
8
0
-
0
0
3.5
-
5
6
0
-
0
0
-
3
-
4
-
UNIT
Write Cycle Time
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
DW
t
DH
t
WHZ
-
-
-
-
-
-
-
-
-
5
12
-
-
-
-
-
-
-
-
6
15
-
-
-
-
-
-
-
-
6
ns
Chip Selection to End of Write
10
11
ns
Address Valid to End of Write
-
10
11
ns
Address Setup Time
0
0
ns
Write Pulse Width
-
-
-
-
10
11
ns
Write Recovery Time
0
0
ns
Data Valid to End of Write
8
8
ns
Data Hold from End of Write
0
0
ns
Write to Output in High Z
Output Disable to Output in High Z
t
OHZ
Output Active from End of Write
-
-
ns
-
3.5
-
4
-
5
-
6
-
7
ns
t
OW
0
-
0
-
0
-
0
-
0
-
ns
* These parameters are sampled but not 100% tested.
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| T14M256A_04 | 制造商:TMT 制造商全稱:TMT 功能描述:32K X 8 HIGH SPEED CMOS STATIC RAM |
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