
AN99-7
Synchronous DC/DC Controller for
Distributed Power Supply Applications
2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
January 4, 2000
2
Theory of Operation
Synchronous Buck Converter
Primary V
power is provided by a synchronous,
voltage-mode pulse width modulated (PWM) controller.
This section has all the features required to build a
high efficiency synchronous buck converter, including
“Power Good” flag, shut-down, and cycle-by-cycle cur-
rent limit.
The output voltage of the synchronous converter is set
and controlled by the output of the error amplifier. The
external resistive divider reference voltage is derived
from an internal trimmed-bandgap voltage reference
(See Fig. 1). The inverting input of the error amplifier
receives its voltage from the SENSE pin.
The internal oscillator uses an on-chip capacitor and
trimmed precision current sources to set the oscillation
frequency to 200kHz. The triangular output of the os-
cillator sets the reference voltage at the inverting input
of the comparator. The non-inverting input of the com-
parator receives it’s input voltage from the error ampli-
fier. When the oscillator output voltage drops below the
error amplifier output voltage, the comparator output
goes high. This pulls DL low, turning off the low-side
FET, and DH is pulled high, turning on the high-side
FET (once the cross-current control allows it). When
the oscillator voltage rises back above the error ampli-
fier output voltage, the comparator output goes low.
This pulls DH low, turning off the high-side FET, and
DL is pulled high, turning on the low-side FET (once
the cross-current control allows it).
As SENSE increases, the output voltage of the error
amplifier decreases. This causes a reduction in the on-
time of the high-side MOSFET connected to DH,
hence lowering the output voltage.
Under Voltage Lockout
The under voltage lockout circuit of the SC1102 as-
sures that the high-side MOSFET driver outputs re-
main in the off state whenever the supply voltage drops
below set parameters. Lockout occurs if V
CC
falls below
4.1V. Normal operation resumes once V
CC
rises above
4.2V.
Over-Voltage Protection
The over-voltage protection pin (OVP) is high only
when the voltage at SENSE is 20% higher than the tar-
get value programmed by the external resistor divider.
The OVP pin is internally connected to an NPN emitter
follower.
Power Good
The power good function is to confirm that the regula-
tor outputs are within +/-10% of the programmed level.
PWRGD remains high as long as this condition is met.
PWRGD is connected to an internal open collector
NPN transistor.
Soft Start
Initially, SS/SHDN sources 10μA of current to charge
an external capacitor. The outputs of the error ampli-
fiers are clamped to a voltage proportional to the volt-
age on SS/SHDN. This limits the on-time of the high-
side MOSFETs, thus leading to a controlled ramp-up of
the output voltages.
R
Current Limiting
The current limit threshold is set by connecting an ex-
ternal resistor from the V
supply to OCSET. The volt-
age drop across this resistor is due to the 200μA inter-
nal sink sets the voltage at the pin. This voltage is
compared to the voltage at the PHASE node. This
comparison is made only when the high-side drive is
high to avoid false current limit triggering due to uncon-
tributing measurements from the MOSFET’s off-
voltage. When the voltage at PHASE is less than the
voltage at OCSET, an overcurrent condition occurs
and the soft start cycle is initiated. The synchronous
switcher turns off and SS/SHDN starts to sink 2μA.
When SS/SHDN reaches 0.8V, it then starts to source
10μA and a new cycle begins.
Hiccup Mode
During power up, the SS/SHDN pin is internally pulled
low until VCC reaches the undervoltage lockout level of
4.2V. Once V
has reached 4.2V, the SS/SHDN pin
is released and begins to source 10μA of current to the
external soft-start capacitor. As the soft-start voltage
rises, the output of the internal error amplifier is
clamped to this voltage. When the error signal
reaches the level of the internal triangular oscillator,
which swings from 1V to 2V at a fixed frequency of 200
kHz, switching occurs. As the error signal crosses
over the oscillator signal, the duty cycle of the PWM
signal continues to increase until the output comes into
regulation. If an over-current condition has not oc-
curred the soft-start voltage will continue to rise and
level off at about 2.2V.
An over-current condition occurs when the high-side
drive is turned on, but the PHASE node does not