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參數(shù)資料
| 型號： | SYM53C860 |
| 廠商： | LSI Corporation |
| 英文描述： | Single-Chip High-Performance PCI-Ultra SCSI (Fast-20) I/O Processor(單片、高性能PCI-超級SCSI (Fast-20) I/O 處理器) |
| 中文描述： | 單芯片高性能的PCI -超的SCSI（快速- 20）I / O處理器（單片，高性能的PCI -超級的SCSI（快速- 20）的I / O處理器） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 38K |
| 代理商： | SYM53C860 |
2
Power Management
The SYM53C860E complies with the PCI Bus Power Management Interface Specification,
Revision 1.0. The PCI Function Power States are defined in that specification: D0, D1, D2, and
D3. D0 and D3 are required by specification and D1 and D2 are optional. D0 is the maximum
powered state, and D3 is the minimum powered state. Power state D3 is further categorized as
D3hot or D3cold. A function that is powered off is said to be in the D3cold power state.
The power states for the SCSI function are independently controlled through two power state bits
that are located in the PCI Configuration Space Register 44h. The bits are encoded as: 00b –
power state D0, 01b – reserved, 10b - reserved, and 11b - power state D3.
The PCI Function Power States--D0 and D3--are described below. Power states D1 and D2 are
not implemented for this device.
Power State D0
Power state D0 is the maximum power state and is the power-up default state for each function.
Power State D3
Power state D3 is the minimum power state, which includes subsettings called D3hot and
D3cold. The devices are considered to be in power state D3cold when power is removed from
them. D3cold can transition to D0 by applying Vcc and resetting the device. D3hot allows the
device to transition to D0 via software. To obtain power reduction in D3hot, the SCSI clock and
the SCSI clock doubler Phase Lock Loop (PLL) are disabled. Furthermore, soft reset is
continually asserted while in power state D3hot, which clears all pending interrupts and tristates
the SCSI bus. In addition, the function’s PCI command register is cleared.
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