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參數(shù)資料
| 型號(hào)： | SY89876LMI TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFF DVDR 1:2 2GHZ 16-MLF |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Precision Edge® |
| 類(lèi)型： | 扇出緩沖器（分配），除法器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，HSTL，LVDS，LVPECL |
| 輸出： | LVDS |
| 頻率 - 最大： | 2GHz |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤(pán)，16-MLF? |
| 供應(yīng)商設(shè)備封裝： | 16-MLF?（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 1084 (CN2011-ZH PDF) |
| 其它名稱(chēng)： | 576-2958-6 |
1
Precision Edge
SY89876L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
Integrated programmable clock divider and 1:2
fanout buffer
Guaranteed AC performance over temperature and
voltage:
>2.0GHz f
MAX
<190ps tr /tf
<15ps within device skew
Low jitter design:
<10ps
PP total jitter
<1ps
RMS cycle-to-cycle jitter
Unique input termination and VT Pin for DC- and AC-
coupled inputs; CML, PECL, LVDS and HSTL
LVDS-compatible outputs
TTL/CMOS inputs for select and reset
Parallel programming capability
Programmable divider ratios of 1, 2, 4, 8 and 16
Low voltage operation 3.3V
Output disable function
–40°C to 85°C industrial temperature range
Available in 16-pin (3mm x 3mm) MLF package
FEATURES
3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS
PROGRAMMABLE CLOCK DIVIDER AND
1:2 FANOUT BUFFER W/ INTERNAL TERMINATION
Precision Edge
SY89876L
APPLICATIONS
SONET/SDH line cards
Transponders
High-end, multiprocessor servers
1
Rev.: E
Amendment: /0
Issue Date:
August 2007
This low-skew, low-jitter device is capable of accepting a
high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS
or HSTL clock input signal and dividing down the frequency
using a programmable divider ratio to create a lower speed
version of the input clock. Available divider ratios are 2, 4, 8
and 16, or straight pass-through.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A V
REF-AC
reference is included for AC-coupled applications.
The /RESET input asynchronously resets the divider. In
the pass-through function (divide by 1) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /IN).
FUNCTIONAL BLOCK DIAGRAM
TYPICAL PERFORMANCE
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
IN
/IN
S1
(TTL/CMOS)
S0
(TTL/CMOS)
Q1
/Q1
Q0
/Q0
50
50
/RESET
(TTL/CMOS)
VT
VREF_AC
S2
(TTL/CMOS)
Divided
by
2, 4, 8
or 16
Enable
MUX
Enable
FF
Decoder
Divide-by-4
CML/LVPECL/LVDS
622MHz
Clock In
OC-12 to OC-3
Translator/Divider
LVDS
155.5MHz
Clock Out
622MHz In
/Q0
Q0
/IN
IN
155.5MHz Out
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