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參數(shù)資料
| 型號： | SY89876LMG |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFF DVDR 1:2 2GHZ 16-MLF |
| 標準包裝： | 100 |
| 系列： | Precision Edge® |
| 類型： | 扇出緩沖器（分配），除法器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，HSTL，LVDS，LVPECL |
| 輸出： | LVDS |
| 頻率 - 最大： | 2GHz |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，16-MLF? |
| 供應商設(shè)備封裝： | 16-MLF?（3x3） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1084 (CN2011-ZH PDF) |
| 其它名稱： | 576-2106-5 SY89876LMG-ND |
5
SY88793V
Micrel, Inc.
M9999-072505
hbwhelp@micrel.com or (408) 955-1690
DETAILED DESCRIPTION
The SY88793V low-power limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from –40
°C to +85°C. Signals with data rates up to 622Mbps
and as small as 5mVp-p can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88793V generates
an SD output. SD
LVL sets the sensitivity of the input
amplitude detection.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the SY88793V's
input stage. The high-sensitivity of the input amplifier allows
signals as small as 5mV
PP to be detected and amplified.
The input amplifier allows input signals as large as
1800mV
PP. Input signals are linearly amplified with a typically
38dB differential voltage gain. Since it is a limiting amplifier,
the SY88793V outputs typically 1500mV
PP voltage-limited
waveforms for input signals that are greater than 18mV
PP.
Applications requiring the SY88793V to operate with high-
gain should have the upstream TIA placed as close as
possible to the SY88793V’s input pins to ensure the best
performance of the device.
Output Buffer
The SY88793V’s PECL output buffer is designed to drive
50
lines. The output buffer requires appropriate termination
for proper operation. An external 50
resistor to V
CC–2V
for each output pin provides this. Figure 3 shows a simplified
schematic of the output stage and includes an appropriate
termination method.
Signal-Detect
The SY88793V generates a chatter-free SD open-collector
TTL output with internal 6.75k
pullup resistor as shown in
Figure 4. SD is used to determine that the input amplitude
is large enough to be considered a valid input. SD asserts
high if the input amplitude rises above the threshold set by
SD
LVL and deasserts low otherwise. SD can be fed back to
the enable (EN) input to maintain output stability under a
loss of signal condition. EN deasserts the true output signal
without removing the input signals. Typically 6dB SD
hysteresis is provided to prevent chattering.
Signal-Detect Level Set
A programmable SD level set pin (SDLVL) sets the
threshold of the input amplitude detection. Connecting an
external resistor between V
CC and SDLVL sets the voltage
at SD
LVL. This voltages ranges from VCC to VREF. The
external resistor creates a voltage divider between V
CC and
V
REF as shown in Figure 5. If desired, an appropriate
external voltage may be applied rather than using a resistor.
The smaller the external resistor, implying a smaller voltage
difference from SD
LVL to VCC, the smaller the SD sensitivity.
Hence, larger input amplitude is required to assert SD.
“Typical Operating Characteristics” shows the relationship
between the input amplitude detection sensitivity and the
SDLVL voltage.
Hysteresis
The SY88793V provides typically 6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V2
IN/R for an
electrical signal. Hence the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and
hence the ratios change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the datasheet. The SY88793V provides typically 3dB SD
optical hysteresis. As the SY88793V is an electrical device,
this datasheet refers to hysteresis in electrical terms. With
6dB SD hysteresis, a voltage factor of two is required to
assert or deassert SD.
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參數(shù)描述 |
|---|---|
| SY89876LMG TR | 功能描述:時鐘驅(qū)動器及分配 3.3V LVDS Output Clock Divider/Fanout (I Temp, Green) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| SY89876LMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER W/ INTERNAL TERMINATION |
| SY89876LMG-TR | 功能描述:Clock Fanout Buffer (Distribution), Divider IC 2GHz 16-VFQFN Exposed Pad, 16-MLF? 制造商:microchip technology 系列:Precision Edge? 包裝:剪切帶（CT） 零件狀態(tài):有效 類型:扇出緩沖器（分配），除法器 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:是/是 輸入:CML，HSTL，LVDS，LVPECL 輸出:LVDS 頻率 - 最大值:2GHz 電壓 - 電源:2.97 V ~ 3.63 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商器件封裝:16-MLF?（3x3） 標準包裝:1 |
| SY89876LMI | 功能描述:IC CLK BUFF DVDR 1:2 2GHZ 16-MLF RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:Precision Edge® 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設(shè)備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| SY89876LMI TR | 功能描述:IC CLK BUFF DVDR 1:2 2GHZ 16-MLF RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:Precision Edge® 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設(shè)備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
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