參數(shù)資料
型號: SY89874UMG TR
廠商: Micrel Inc
文件頁數(shù): 4/11頁
文件大小: 0K
描述: IC CLOCK BUFF DIVIDER 1:2 16-MLF
標(biāo)準(zhǔn)包裝: 1,000
系列: Precision Edge®
類型: 扇出緩沖器(分配),除法器
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
輸入: CML,HSTL,LVDS,LVPECL
輸出: LVPECL
頻率 - 最大: 2.5GHz
電源電壓: 2.375 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,16-MLF?
供應(yīng)商設(shè)備封裝: 16-MLF?(3x3)
包裝: 帶卷 (TR)
其它名稱: SY89874UMGTR
SY89874UMGTR-ND
Micrel, Inc.
SY89874U
October 1, 2013
2
Revision 1.1
hbwhelp@micrel.com or (408) 955-1690
Ordering Information
Part Number(1)
Package Type
Operating Range
Package Marking
Lead Finish
SY89874UMG
QFN-16
Industrial
874U with Pb-free
bar-line indicator
NiPdAu
SY89874UMGTR(2)
QFN-16
Industrial
874U with Pb-free
bar-line indicator
NiPdAu
Note:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Tape and Reel.
Pin Configuration
16-Pin QFN
Pin Description
Pin Number
Pin Name
Pin Function
12, 9
IN, /IN
Differential input. Internal 50 termination resistors to VT input. Flexible input accepts any
differential input. See the Input Interface Applications section.
1, 2, 3, 4
Q0, /Q0
Q1, /Q1
Differential buffered LVPECL Outputs. Divided by 1, 2, 4, 8, or 16. See Truth Table. Unused
PECL outputs may be left floating with no impact on jitter performance.
16, 15, 5
S0, S1, S2
Select pins. See Truth Table. LVTTL/CMOS logic levels. Internal 25k pull-up resistor. Logic
HIGH if left unconnected (divided by 16 mode). Input threshold is VCC/2.
6
NC
No connect.
8
/RESET
/DISABLE
LVTTL/CMOS logic levels. Internal 25k pull-up resistor. Logic HIGH if left unconnected. Apply
LOW to reset the divider (divided by 2, 4, 8, or 16 mode). Also acts as a synchronous
disable/enable function. The reset and disable function occurs on the next HIGH-to-LOW clock
input transition. Input threshold is VCC/2.
10
VREF-AC
Reference voltage. Equal to VCC-1.4V (approximately). Used for AC-coupled applications only.
Decouple the VREF-AC pin with a 0.01F capacitor. See the Input Interface Applications section.
11
VT
Termination center tap. For CML or LVDS inputs, leave this floating. Otherwise, see Figures 2a to
2f within the Input Interface Applications section.
7, 14
VCC
Positive power supply. Bypass with .01F /0.01F low-ESR capacitor.
13
GND
Ground.
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