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參數(shù)資料
| 型號(hào)： | SY89858U |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | PRECISION CML RUNT PULSE ELIMINATOR 2:1 MUX WITH 1:2 FANOUT AND INTERNAL TERMINATION |
| 中文描述： | 精密白血病短脈沖消除2:1 1:2扇出和內(nèi)部終端復(fù)用器 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 956K |
| 代理商： | SY89858U |
Micrel
SY89858U
November 2004
M9999-110504
hbwhelp@micrel.com
or (408) 955-1690
5
LVPECL Outputs DC Electrical Characteristics
(7)
V
CC
= 2.5V ±5% or 3.3V ±10%; T
A
= –40°C to + 85°C; R
L
= 50 to V
CC
–2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
OH
Output HIGH Voltage
Q, /Q
V
CC
–1.145
V
CC
–0.895
V
V
OL
Output LOW Voltage
Q, /Q
V
CC
–1.945
V
CC
–1.695
V
V
OUT
Output Voltage Swing
Q, /Q
See Figure 1a.
500
800
mV
V
DIFF-OUT
Differential Output Voltage Swing
Q, /Q
See Figure 1b.
1000
1600
mV
Note:
7.
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
AC Electrical Characteristics
(8)
V
CC
= 2.5V ±5% or 3.3V ±10%; T
A
= –40°C to + 85°C, R
L
= 50 to V
CC
–2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Operating Frequency
V
OUT
400mV
2.0
3.0
GHz
t
PD
Propagation Delay (IN-to-Q)
180
260
380
ps
T
pd
Tempco
Differential Propagation Delay
Temperature Coefficient
115
fs/
o
C
Output-to-Output Skew
Note 9
30
T
skew
Part-to-Part Skew
Note 10
150
ps
Random Jitter (RJ)
Note 11
1
ps
(rms)
Deterministic Jitter (DJ)
Note 12
10
ps
(pp)
Cycle-to-Cycle Jitter
Note 13
1
ps
(pp)
t
Jitter
Total Jitter
Note 14
10
ps
(pp)
t
R,
t
F
Output Rise/Fall Time (20% to 80%)
At full output swing.
75
130
200
ps
Notes:
8.
High-frequency AC-parameters are guaranteed by design and characterization.
9.
Output-to-output skew is measured between outputs under identical conditions.
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs. Part-to-part skew includes variation in t
pd
.
11. Random jitter is measured with a K28.7 character pattern, measured at 2.5Gbps.
12. Deterministic Jitter is measured at 2.5Gbps, with both K28.5 and 2
23
– 1 PRBS pattern.
13. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, T
n
– T
n-1
where T is the time between rising edges of the
output signal.
14. Total jitter definition: With an ideal clock input of frequency <f
MAX
, no more than one output edge in 10
12
output edges will deviate by more
than the specified peak-to-peak jitter value.
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