hbwhelp@micrel.com or (408) 955-1690 Ordering Inform" />
參數(shù)資料
型號(hào): SY89855UMG
廠商: Micrel Inc
文件頁(yè)數(shù): 7/13頁(yè)
文件大小: 0K
描述: IC MUX 4:1 LVPECL PREC LP 32-MLF
標(biāo)準(zhǔn)包裝: 60
系列: SY89
類(lèi)型: 多路復(fù)用器
電路: 1 x 4:1
獨(dú)立電路: 1
電壓電源: 單電源
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán),32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1090 (CN2011-ZH PDF)
其它名稱(chēng): 576-2101-5
SY89855UMG-ND
Micrel, Inc.
SY89855U
August 2007
3
M9999-082907-C
hbwhelp@micrel.com or (408) 955-1690
Ordering Information
(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead Finish
SY89855UMG
QFN-32
Industrial
SY89855U with Pb-Free bar-line indicator
NiPdAu Pb-Free
SY89855UMGTR
(2)
QFN-32
Industrial
SY89855U with Pb-Free bar-line indicator
NiPdAu Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
32-Pin QFN
Pin Description
Pin Number
Pin Name
Pin Function
1, 4
5, 8
25, 28
29, 32
IN0, /IN0,
IN1, /IN1,
IN2, /IN2,
IN3, /IN3
Differential Input: Each pair accepts AC- or DC-coupled signals as small as 100mV. Each
pin of a pair internally terminates to a VT pin through 50. Note that these inputs will
default to an indeterminate state if left open. If an input is not used, connect one end of the
differential pairs to ground through a 1k resistor, and leave the other end to VCC through
an 825 resistor. Unused VT and VREF-AC pins may also be left floating. Please refer to
the “Input Interface Applications” section for more details.
2, 6
26, 30
VT0, VT1
VT2, VT3
Input Termination Center-Tap: Each side of the differential input pair terminates to a VT
pin. The VT pin provides a center-tap to the termination network for maximum interface
flexibility. See “Input Interface Applications” section for more details.
15, 18
SEL0, SEL1
This Single-Ended TTL/CMOS compatible input selects the inputs to the multiplexer. Note
that this input is internally connected to a 25k pull-up resistor and will default to a logic
HIGH state if left open. Input logic threshold is VCC/2. See “Truth Table” for select control.
14, 19
NC
Not connected.
10, 13, 16
17, 20, 23
VCC
Positive Power Supply: Bypass with 0.1F||0.01F low ESR capacitors placed as close as
possible to each VCC pin.
11, 12
21, 22
/Q0, Q0
/Q1, Q1
Differential Outputs: These 100K-compatible (internally temperature compensated)
LVPECL output pairs are copies of the selected input. Unused output pins may be left
floating. See “Output Interface” for terminating guidelines.
9, 24
GND,
Exposed Pad
Ground: Ground pins and exposed pad must be connected to the most negative potential
of the chip.
3
7
27
31
VREF-AC0,
VREF-AC1,
VREF-AC2,
VREF-AC3
Reference Voltage: This reference output is equivalent to VCC–1.2V. It is used for AC-
coupled inputs. When interfacing to AC input signals, connect VREF-AC directly to the VT
pin and bypass with a 0.01F low ESR capacitor to VCC. See “Input Interface
Applications” section. Maximum sink/source current is ± 1.5mA.
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