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參數(shù)資料
| 型號(hào)： | SY898533LKZ |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:4 20-TSSOP |
| 特色產(chǎn)品： | SY898533L Fanout Buffer |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 系列： | Precision Edge® |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，HCSL，LVDS，LVHSTL，LVPECL，SSTL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 650MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1091 (CN2011-ZH PDF) |
| 其它名稱： | 576-3560-5 |
5
SY88883V
Micrel, Inc.
M9999-081005
hbwhelp@micrel.com or (408) 955-1690
DETAILED DESCRIPTION
The SY88883V low-power limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from –40
°C to +85°C. Signals with data rates up to 3.2Gbps
and as small as 10mVPP can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88883V generates
an SD output. SD
LVL sets the sensitivity of the input
amplitude detection.
Input Amplifier/Buffer
The SY88883V’s inputs are internally terminated with 50
to an internal reference voltage (V
REF). VREF is typically
1.3V below V
CC. Unless not affected by this internal
termination scheme, upstream devices need to be
AC-coupled to the SY88883V’s inputs. Figure 2 shows a
simplified schematic of the input stage.
The high-sensitivity of the input amplifier allows signals
as small as 10mVPP to be detected and amplified. The
input amplifier allows input signals as large as 1800mVPP.
Input signals are linearly amplified with a typically 38dB
differential voltage gain. Since it is a limiting amplifier, the
SY88883V outputs typically 800mVPP voltage-limited
waveforms for input signals that are greater than 10mVPP.
Applications requiring the SY88883V to operate with high-
gain should have the upstream TIA placed as close as
possible to the SY88883V’s input pins to ensure the best
performance of the device.
Output Buffer
The SY88883V’s CML output buffer is designed to drive
50
lines. The output buffer requires appropriate termination
for proper operation. An external 50
resistor to V
CC or
equivalent for each output pin provides this. Figure 3 shows
a simplified schematic of the output stage and includes an
appropriate termination method. Of course, driving a
downstream device with a CML input that is internally
terminated with 50
to V
CC eliminates the need for external
termination. As noted in the previous section, the amplifier
outputs typically 800mVPP waveforms across 25 total
loads. The output buffer, thus, switches typically 16mA tail-
current. Figure 4 shows the power supply current
measurement which excludes the 16mA tail-current.
Signal Detect
The SY88883V generates a chatter-free signal detect
(SD) open-collector TTL output with internal 5k
pull-up
resistor as shown in Figure 5. SD is used to determine that
the input amplitude large enough to be considered a valid
input. SD asserts high if the input amplitude rises above the
threshold set by SD
LVL and deasserts low otherwise.
Typically 4.6dB SD hysteresis is provided to prevent
chattering.
Signal Detect-Level Set
A programmable signal detect-level set pin (SD
LVL) sets
the threshold of the input amplitude detection. Connecting
an external resistor between V
CC and SDLVL sets the voltage
at SD
LVL. This voltage ranges from VCC to VREF. The
external resistor creates a voltage divider between V
CC and
V
REF as shown in Figure 6. If desired, an appropriate
external voltage may be applied rather than using a resistor.
The smaller the external resistor, implying a smaller voltage
difference from SD
LVL to VCC, lowers the SD sensitivity.
Hence, larger input amplitude is required to assert SD.
“Typical Operating Characteristics” shows the relationship
between the input amplitude detection sensitivity and the
SD
LVL setting resistor.
Hysteresis
The SY88883V provides typically 4.6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V2
IN/R for an
electrical signal. Hence, the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and,
hence, the ratios change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the data sheet. The SY88883V provides typically 2.3dB
SD optical hysteresis. As the SY88883V is an electrical
device, this data sheet refers to hysteresis in electrical terms.
With 4.6dB SD hysteresis, a voltage factor of 1.7 is required
to assert SD from its deassert level.
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| SY898533LKZ TR | 功能描述:緩沖器和線路驅(qū)動(dòng)器 3.3V LVPECL 1:4 Fanout Buffer RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SY898533LKZTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision Differential 3.3V Low Skew LVPECL 1:4 Fanout Buffer |
| SY898535L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision Differential 3.3V, Low Skew, 1:4 LVCMOS/LVTTL -to-LVPECL Fanout Buffer |
| SY898535LKY | 功能描述:緩沖器和線路驅(qū)動(dòng)器 1:4 LVPECL Fanout Buffer, 2 LVCMOS Input RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SY898535LKY TR | 功能描述:緩沖器和線路驅(qū)動(dòng)器 1:4 LVPECL Fanout Buffer, 2 LVCMOS Input RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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